URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [peripheral/] [mc.c] - Diff between revs 970 and 997

Rev 970	Rev 997
Line 139...	Line 139...
`void mc_reset()`	`void mc_reset()`
`{`	`{`
`struct dev_memarea *mem_dev = dev_list;`	`struct dev_memarea *mem_dev = dev_list;`

`if (config.mc.enabled) {`	`if (config.mc.enabled) {`
`printf("Resetting memory controller.\n");`	`PRINTF("Resetting memory controller.\n");`
`memset(&mc, 0, sizeof(struct mc));`	`memset(&mc, 0, sizeof(struct mc));`

`mc.poc = config.mc.POC;`	`mc.poc = config.mc.POC;`

`/* Set CS0 */`	`/* Set CS0 */`
Line 176...	Line 176...

`void mc_status()`	`void mc_status()`
`{`	`{`
`int i;`	`int i;`

`printf( "\nMemory Controller at 0x%08X:\n", config.mc.baseaddr );`	`PRINTF( "\nMemory Controller at 0x%08X:\n", config.mc.baseaddr );`
`printf( "POC: 0x%08X\n", mc.poc );`	`PRINTF( "POC: 0x%08X\n", mc.poc );`
`printf( "BAS: 0x%08X\n", mc.ba_mask );`	`PRINTF( "BAS: 0x%08X\n", mc.ba_mask );`
`printf( "CSR: 0x%08X\n", mc.csr );`	`PRINTF( "CSR: 0x%08X\n", mc.csr );`

`for (i=0; i<N_CE; i++) {`	`for (i=0; i<N_CE; i++) {`
`printf( "CE %02d - CSC: 0x%08X TMS: 0x%08X\n", i, mc.csc[i], mc.tms[i]);`	`PRINTF( "CE %02d - CSC: 0x%08X TMS: 0x%08X\n", i, mc.csc[i], mc.tms[i]);`
`}`	`}`
`}`	`}`

`No newline at end of file`	`No newline at end of file`