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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [sim.cfg] - Diff between revs 1461 and 1486

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Rev 1461	Rev 1486
Line 72...	Line 72...
`pattern to fill memory, used if type = 'pattern'.`	`pattern to fill memory, used if type = 'pattern'.`

`nmemories =`	`nmemories =`
`number of memory instances connected`	`number of memory instances connected`

`instance specific:`
`baseaddr =`	`baseaddr =`
`memory start address`	`memory start address`

`size =`	`size =`
`memory size`	`memory size`
Line 85...	Line 84...
`memory block name`	`memory block name`

`ce =`	`ce =`
`chip enable index of the memory instance`	`chip enable index of the memory instance`

	`mc =`
	`memory controller this memory is connected to`

`delayr =`	`delayr =`
`cycles, required for read access, -1 if instance does not support reading`	`cycles, required for read access, -1 if instance does not support reading`

`delayw =`	`delayw =`
`cycles, required for write access, -1 if instance does not support writing`	`cycles, required for write access, -1 if instance does not support writing`
Line 102...	Line 104...
`/*random_seed = 12345`	`/*random_seed = 12345`
`type = random*/`	`type = random*/`
`pattern = 0x00`	`pattern = 0x00`
`type = unknown /* Fastest */`	`type = unknown /* Fastest */`


`nmemories = 3`
`device 0`
`name = "FLASH"`	`name = "FLASH"`
`ce = 0`	`ce = 0`
	`mc = 0`
`baseaddr = 0xf0000000`	`baseaddr = 0xf0000000`
`size = 0x00800000`	`size = 0x00800000`
`delayr = 10`	`delayr = 10`
`delayw = -1`	`delayw = -1`
`enddevice`	`end`

	`section memory`
	`/*random_seed = 12345`
	`type = random*/`
	`pattern = 0x00`
	`type = unknown /* Fastest */`

`device 1`
`name = "RAM"`	`name = "RAM"`
`ce = 1`	`ce = 1`
	`mc = 0`
`baseaddr = 0x00000000`	`baseaddr = 0x00000000`
`size = 0x00400000`	`size = 0x00400000`
`delayr = 1`	`delayr = 1`
`delayw = 2`	`delayw = 2`
`enddevice`	`end`

	`section memory`
	`/*random_seed = 12345`
	`type = random*/`
	`pattern = 0x00`
	`type = unknown /* Fastest */`

`device 2`
`name = "SRAM"`	`name = "SRAM"`
	`mc = 0`
`ce = 2`	`ce = 2`
`baseaddr = 0x08000000`	`baseaddr = 0x08000000`
`size = 0x00400000`	`size = 0x00400000`
`delayr = 1`	`delayr = 1`
`delayw = 2`	`delayw = 2`
`enddevice`
`end`	`end`


`/* IMMU SECTION`	`/* IMMU SECTION`

Line 565...	Line 576...
`baseaddr =`	`baseaddr =`
`address of first MC register`	`address of first MC register`

`POC =`	`POC =`
`Power On Configuration register`	`Power On Configuration register`

	`index =`
	`Index of this memory controller amongst all the memory controllers`
`*/`	`*/`

`section mc`	`section mc`
`enabled = 1`	`enabled = 1`
`baseaddr = 0x93000000`	`baseaddr = 0x93000000`
`POC = 0x00000008 /* Power on configuration register */`	`POC = 0x00000008 /* Power on configuration register */`
	`index = 0`
`end`	`end`


`/* UART SECTION`	`/* UART SECTION`

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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [sim.cfg] - Diff between revs 1461 and 1486