URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [sim.cfg] - Diff between revs 294 and 304

Rev 294	Rev 304
Line 33...	Line 33...
`hazards = 0`	`hazards = 0`
`history = 0`	`history = 0`
`dependstats = 0`	`dependstats = 0`
`dependency = 0`	`dependency = 0`
`slp = 0`	`slp = 0`
`btic_sim = 0`	`btic = 0`
`bpb = 0`	`bpb = 0`
`end`	`end`

`section debug`	`section debug`
`/*enabled = 0`	`/*enabled = 0`
Line 49...	Line 49...
`debug = 0`	`debug = 0`
`profile = 0`	`profile = 0`
`prof_fn = "sim.profile"`	`prof_fn = "sim.profile"`

`/* iprompt = 0 */`	`/* iprompt = 0 */`
`exe_log = 1`	`exe_log = 0`
`exe_log_fn = "executed.log"`	`exe_log_fn = "executed.log"`
`end`	`end`

`section mc`	`section mc`
`enabled = 1`	`enabled = 0`
`baseaddr = 0xa0000000`	`baseaddr = 0xa0000000`
`POC = 0x00000008 /* Power on configuration register */`	`POC = 0x00000008 /* Power on configuration register */`
`end`	`end`

`section uart`	`section uart`
`enabled = 1`	`enabled = 0`
`nuarts = 1`	`nuarts = 1`

`device 0`	`device 0`
`baseaddr = 0x80000000`	`baseaddr = 0x80000000`
`rxfile = "/tmp/uart0.rx"`	`rxfile = "/tmp/uart0.rx"`
Line 72...	Line 72...
`jitter = -1 /* async behaviour */`	`jitter = -1 /* async behaviour */`
`enddevice`	`enddevice`
`end`	`end`

`section dma`	`section dma`
`enabled = 1`	`enabled = 0`
`ndmas = 1`	`ndmas = 1`

`device 0`	`device 0`
`baseaddr = 0x90000000`	`baseaddr = 0x90000000`
`irq = 4`	`irq = 4`
`enddevice`	`enddevice`
`end`	`end`

`section VAPI`	`section VAPI`
`enabled = 0`	`enabled = 0`
	`server_port = 9998`
	`end`

	`section ethernet`
	`enabled = 0`
`end`	`end`