URL
https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [sim.cfg] - Diff between revs 383 and 384
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 383 |
Rev 384 |
| Line 61... |
Line 61... |
Memory table file structure is as follows:
|
Memory table file structure is as follows:
|
>start_address1 length1 type1 [ce1 [delayr1 [delayw1]]]
|
>start_address1 length1 type1 [ce1 [delayr1 [delayw1]]]
|
>start_address2 length2 type2 [ce2 [delayr2 [delayw2]]]
|
>start_address2 length2 type2 [ce2 [delayr2 [delayw2]]]
|
>start_address3 length3 type3 [ce3 [delayr3 [delayw3]]]
|
>start_address3 length3 type3 [ce3 [delayr3 [delayw3]]]
|
|
|
|
(each line start with '>')
|
Example:
|
Example:
|
>00000100 00001F00 flash 3 100
|
>00000100 00001F00 flash 3 100
|
>80000000 00010000 RAM
|
>80000000 00010000 RAM
|
|
|
type = random/unknown/pattern
|
type = random/unknown/pattern
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
