URL
https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [toplevel.c] - Diff between revs 426 and 427
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 426 |
Rev 427 |
Line 50... |
Line 50... |
#include "coff.h"
|
#include "coff.h"
|
|
|
#include "gdbcomm.h"
|
#include "gdbcomm.h"
|
|
|
/* CVS revision number. */
|
/* CVS revision number. */
|
const char rcsrev[] = "$Revision: 1.50 $";
|
const char rcsrev[] = "$Revision: 1.51 $";
|
|
|
/* Continuos run versus single step tracing switch. */
|
/* Continuos run versus single step tracing switch. */
|
int cont_run;
|
int cont_run;
|
|
|
/* History of execution */
|
/* History of execution */
|
Line 275... |
Line 275... |
runtime.sim.init = 0;
|
runtime.sim.init = 0;
|
}
|
}
|
|
|
/* Display info about various modules */
|
/* Display info about various modules */
|
void sim_info () {
|
void sim_info () {
|
|
sprs_status();
|
|
memory_table_status ();
|
itlb_status(-1);
|
itlb_status(-1);
|
dtlb_status(-1);
|
dtlb_status(-1);
|
ic_info();
|
ic_info();
|
dc_info();
|
dc_info();
|
sprs_status();
|
|
|
|
if (config.cpu.bpb) bpb_info();
|
if (config.cpu.bpb) bpb_info();
|
if (config.cpu.btic) btic_info();
|
if (config.cpu.btic) btic_info();
|
if (config.uarts_enabled) uart_status();
|
if (config.uarts_enabled) uart_status();
|
if (config.dmas_enabled) dma_status();
|
if (config.dmas_enabled) dma_status();
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.