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Line 49... |
#include "gdbcomm.h"
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#include "gdbcomm.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "coff.h"
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#include "coff.h"
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/* CVS revision number. */
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/* CVS revision number. */
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const char rcsrev[] = "$Revision: 1.58 $";
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const char rcsrev[] = "$Revision: 1.59 $";
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/* Continuos run versus single step tracing switch. */
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/* Continuos run versus single step tracing switch. */
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int cont_run;
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int cont_run;
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/* History of execution */
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/* History of execution */
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Line 605... |
printf("%s: Unknown command.\n", linestr);
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printf("%s: Unknown command.\n", linestr);
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/* MM: 'run -1' means endless execution. */
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/* MM: 'run -1' means endless execution. */
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while(cont_run != 0) {
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while(cont_run != 0) {
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int debug_slowdown = DEBUG_SLOWDOWN;
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int debug_slowdown = DEBUG_SLOWDOWN;
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extern int mem_cycles;
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if (cpu_stalled) {
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if (cpu_stalled) {
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printf ("!");
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printf ("!");
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if(GDB_ENABLED) {
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if(GDB_ENABLED) {
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BlockJTAG();
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BlockJTAG();
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Line 617... |
} else
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} else
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fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.");
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fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.");
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continue;
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continue;
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}
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}
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/* Each cycle has counter of mem_cycles; this value is joined with cycles
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at the end of the cycle; no sim originated memory accesses should be
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performed inbetween. */
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mem_cycles = 0;
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if (!testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
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if (!testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
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pic_clock();
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pic_clock();
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if (cont_run > 0) cont_run--;
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if (cont_run > 0) cont_run--;
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if(fetch()) {
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if(fetch()) {
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printf ("Breakpoint hit.\n");
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printf ("Breakpoint hit.\n");
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Line 632... |
break;
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break;
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}
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}
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decode_execute(&iqueue[0]);
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decode_execute(&iqueue[0]);
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update_pc();
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update_pc();
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analysis();
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analysis();
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if (!hush)
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dumpreg();
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dc_clock();
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dc_clock();
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ic_clock();
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ic_clock();
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if (!testsprbits(SPR_PMR, SPR_PMR_SME)) tick_clock();
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if (!testsprbits(SPR_PMR, SPR_PMR_SME)) tick_clock();
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}
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}
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pm_clock();
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pm_clock();
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if (config.uarts_enabled) uart_clock();
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if (config.uarts_enabled) uart_clock();
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if (config.dmas_enabled) dma_clock();
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if (config.dmas_enabled) dma_clock();
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if (config.ethernets_enabled) eth_clock();
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if (config.ethernets_enabled) eth_clock();
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if (config.gpios_enabled) gpio_clock();
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if (config.gpios_enabled) gpio_clock();
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if (config.sim.exe_log) dump_exe_log();
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if (config.vapi.enabled) vapi_check();
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if (config.vapi.enabled) vapi_check();
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if (GDB_ENABLED) {// && ((debug_slowdown--) <= 0)) {
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if (GDB_ENABLED) {// && ((debug_slowdown--) <= 0)) {
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debug_slowdown = DEBUG_SLOWDOWN;
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debug_slowdown = DEBUG_SLOWDOWN;
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HandleServerSocket(false); /* block & check_stdin = false */
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HandleServerSocket(false); /* block & check_stdin = false */
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debug (1, ".");
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debug (1, ".");
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}
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}
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if (DEBUG_ENABLED)
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if (DEBUG_ENABLED)
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if (testsprbits(SPR_DMR1, SPR_DMR1_ST)) set_stall_state (1);
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if (testsprbits(SPR_DMR1, SPR_DMR1_ST)) set_stall_state (1);
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cycles += mem_cycles;
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if (!hush) dumpreg();
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if (config.sim.exe_log) dump_exe_log();
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}
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}
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hush = 0;
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hush = 0;
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fflush(stdout);
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fflush(stdout);
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freopen("/dev/fd/0", "w+", stdout);
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freopen("/dev/fd/0", "w+", stdout);
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