| Line 28... |
Line 28... |
#include <stdlib.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <unistd.h>
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#include <signal.h>
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#include <signal.h>
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#include <stdarg.h>
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#include <stdarg.h>
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#include <fcntl.h>
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#include <fcntl.h>
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#include <limits.h>
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#ifdef HAVE_LIBREADLINE
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#ifdef HAVE_LIBREADLINE
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#include <readline/readline.h>
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#include <readline/readline.h>
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#include <readline/history.h>
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#include <readline/history.h>
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#endif /* HAVE_LIBREADLINE */
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#endif /* HAVE_LIBREADLINE */
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| Line 50... |
Line 51... |
#include "ps2kbd.h"
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#include "ps2kbd.h"
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#include "vapi.h"
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#include "vapi.h"
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#include "gdbcomm.h"
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#include "gdbcomm.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "coff.h"
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#include "coff.h"
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#include "sched.h"
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#include "profiler.h"
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#include "profiler.h"
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#include "mprofiler.h"
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#include "mprofiler.h"
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/* CVS revision number. */
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/* CVS revision number. */
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const char rcsrev[] = "$Revision: 1.78 $";
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const char rcsrev[] = "$Revision: 1.79 $";
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/* Continuos run versus single step tracing switch. */
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/* Continuos run versus single step tracing switch. */
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int cont_run;
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int cont_run;
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/* History of execution */
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/* History of execution */
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| Line 162... |
Line 163... |
void debugmem (unsigned long from, unsigned long to );
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void debugmem (unsigned long from, unsigned long to );
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/* Resets all subunits */
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/* Resets all subunits */
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void sim_reset ()
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void sim_reset ()
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{
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{
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SCHED_INIT();
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uart_reset();
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uart_reset();
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dma_reset();
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dma_reset();
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eth_reset();
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eth_reset();
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gpio_reset();
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gpio_reset();
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vga_reset ();
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vga_reset ();
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| Line 366... |
Line 368... |
if (runtime.vapi.enabled) vapi_done ();
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if (runtime.vapi.enabled) vapi_done ();
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done_memory_table ();
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done_memory_table ();
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exit(0);
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exit(0);
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}
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}
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/* Executes jobs in time queue */
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static inline void do_scheduler ()
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{
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void (*func)(int);
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int param;
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/* Execute all jobs till now */
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do {
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func = SCHED_PEEK().func;
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param = SCHED_PEEK().param;
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SCHED_REMOVE();
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func (param);
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} while (cycles >= SCHED_PEEK().time);
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}
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/*###############################################
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/* Main function */
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| MAIN
|
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###############################################*/
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int main(argc, argv)
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int main(argc, argv)
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int argc;
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int argc;
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char *argv[];
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char *argv[];
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{
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{
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char *linestr;
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char *linestr;
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| Line 699... |
Line 712... |
at the end of the cycle; no sim originated memory accesses should be
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at the end of the cycle; no sim originated memory accesses should be
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performed inbetween. */
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performed inbetween. */
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mem_cycles = 0;
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mem_cycles = 0;
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if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
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if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
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if (cont_run > 0) cont_run--;
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if (cont_run > 0) cont_run--;
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if (config.pm.enabled) {
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if (!testsprbits(SPR_PMR, SPR_PMR_SME))
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IFF (config.tick.enabled) tick_clock();
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} else
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IFF (config.tick.enabled) tick_clock();
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pic_clock ();
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pic_clock ();
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if (cpu_clock ()) break;
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if (cpu_clock ()) break;
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if (config.dc.enabled) dc_clock();
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if (config.dc.enabled) dc_clock();
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if (config.ic.enabled) ic_clock();
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if (config.ic.enabled) ic_clock();
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}
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}
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| Line 724... |
Line 732... |
if (config.debug.gdb_enabled) HandleServerSocket(false); /* block & check_stdin = false */
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if (config.debug.gdb_enabled) HandleServerSocket(false); /* block & check_stdin = false */
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IFF(config.debug.enabled)
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IFF(config.debug.enabled)
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if (testsprbits(SPR_DMR1, SPR_DMR1_ST)) set_stall_state (1);
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if (testsprbits(SPR_DMR1, SPR_DMR1_ST)) set_stall_state (1);
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cycles += mem_cycles;
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cycles += mem_cycles;
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if (cycles >= SCHED_PEEK().time) do_scheduler ();
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if (!hush) dumpreg();
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if (!hush) dumpreg();
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}
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}
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hush = 0;
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hush = 0;
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fflush(stdout);
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fflush(stdout);
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freopen("/dev/fd/0", "w+", stdout);
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freopen("/dev/fd/0", "w+", stdout);
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