| Line 130... |
Line 130... |
#define CPUCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
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#define CPUCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
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#define DCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 7)
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#define DCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 7)
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#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 16)
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#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 16)
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#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 17)
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#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 17)
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#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid))
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#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid))
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#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 32)
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#define EPCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 32 + (cid))
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#define DCR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 40)
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#define EPCR0_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 32)
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#define DMR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 48)
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#define DMR2_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 49)
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#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 0xee)
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#define DCWR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 50)
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#define DCR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 0xee)
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#define DCWR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 51)
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#define DMR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 16)
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#define DSR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 52)
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#define DMR2_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 17)
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#define DRR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 53)
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#define DCWR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 0xee)
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#define DIR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 54)
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#define DCWR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 0xee)
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#define DSR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 20)
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#define DRR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 21)
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#define ZERO_REGNUM (0)
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#define ZERO_REGNUM (0)
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#define SP_REGNUM (1)
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#define SP_REGNUM (1)
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#define FP_REGNUM (2)
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#define FP_REGNUM (2)
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#define A0_REGNUM (3)
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#define A0_REGNUM (3)
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#define A5_REGNUM (8)
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#define A5_REGNUM (8)
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| Line 151... |
Line 154... |
#define VFA0_REGNUM (MAX_GPR_REGS + 0)
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#define VFA0_REGNUM (MAX_GPR_REGS + 0)
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#define VFA5_REGNUM (MAX_GPR_REGS + 5)
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#define VFA5_REGNUM (MAX_GPR_REGS + 5)
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#define VFRV_REGNUM (MAX_GPR_REGS + 6)
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#define VFRV_REGNUM (MAX_GPR_REGS + 6)
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#define PC_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 0)
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#define PC_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 0)
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#define PS_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 1)
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#define PS_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 1)
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#define EPCR_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 2)
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#define CCR_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 2)
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#define CCR_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 2)
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/*******************************************/
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/*******************************************/
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/* Added by CZ on 12/09/01 Used for new style breakpoints */
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/* Added by CZ on 12/09/01 Used for new style breakpoints */
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/* These really aren't designed to be seen by the user */
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/* These really aren't designed to be seen by the user */
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| Line 175... |
Line 179... |
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/* Defines for SPR bits. */
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/* Defines for SPR bits. */
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#define DMR1_ST (0x00400000)
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#define DMR1_ST (0x00400000)
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|
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/* Changed by CZ 21/06/01 */
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/* Changed by CZ 21/06/01 */
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#define DRR_SS (0x00004000)
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#define DRR_BE2 (0x00002000)
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#define DRR_TE (0x00002000)
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#define DRR_BE (0x00001000)
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#define DRR_BE (0x00001000)
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#define DRR_SCE (0x00000800)
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#define DRR_SCE (0x00000800)
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#define DRR_RE (0x00000400)
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#define DRR_RE (0x00000400)
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#define DRR_IME (0x00000200)
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#define DRR_IME (0x00000200)
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#define DRR_DME (0x00000100)
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#define DRR_DME (0x00000100)
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| Line 280... |
Line 283... |
register N. */
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register N. */
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#define REGISTER_BYTE(N) ((N) * OR1K_SPR_REGSIZE)
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#define REGISTER_BYTE(N) ((N) * OR1K_SPR_REGSIZE)
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/* Total amount of space needed to store our copies of the machine's
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'. */
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register state, the array `registers'. */
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#define REGISTER_BYTES (NUM_REGS * OR1K_SPR_REGSIZE)
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#define REGISTER_BYTES (NUM_REGS * OR1K_GPR_REGSIZE)
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extern void or1k_do_registers_info PARAMS ((int, int));
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extern void or1k_do_registers_info PARAMS ((int, int));
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#define DO_REGISTERS_INFO(regnum, fp) or1k_do_registers_info(regnum, fp)
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#define DO_REGISTERS_INFO(regnum, fp) or1k_do_registers_info(regnum, fp)
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| Line 517... |
Line 520... |
TARGET_DISCONNECTING,
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TARGET_DISCONNECTING,
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TARGET_RUNNING,
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TARGET_RUNNING,
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TARGET_STOPPED
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TARGET_STOPPED
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};
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};
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#define REG_SPACE 0x00000000
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#define REG_SPACE_END 0x7FFFFFFF
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#define MEM_SPACE 0x80000000
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#define MEM_SPACE_END 0xFFFFFFFF
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/* Compare conditions for DCRx registers. */
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/* Compare conditions for DCRx registers. */
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enum enum_compare_condition
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enum enum_compare_condition
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{
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{
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CC_MASKED, CC_EQUAL, CC_LESS, CC_LESSE, CC_GREAT, CC_GREATE, CC_NEQUAL
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CC_MASKED, CC_EQUAL, CC_LESS, CC_LESSE, CC_GREAT, CC_GREATE, CC_NEQUAL
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};
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};
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| Line 672... |
Line 670... |
{
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{
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SC_GLOBAL, /* 0 Global BS Chain */
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SC_GLOBAL, /* 0 Global BS Chain */
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SC_RISC_DEBUG, /* 1 RISC Debug Interface chain */
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SC_RISC_DEBUG, /* 1 RISC Debug Interface chain */
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SC_RISC_TEST, /* 2 RISC Test Chain */
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SC_RISC_TEST, /* 2 RISC Test Chain */
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SC_TRACE, /* 3 Trace Chain */
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SC_TRACE, /* 3 Trace Chain */
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SC_REGISTER, /* Register Chain */
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SC_REGISTER, /* 4 Register Chain */
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SC_BLOCK, /* Block Chains */
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SC_WISHBONE, /* 5 Wisbone Chain */
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SC_BLOCK /* Block Chains */
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};
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};
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/* See JTAG documentation about these. */
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/* See JTAG documentation about these. */
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#define JI_SIZE (4)
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#define JI_SIZE (4)
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enum jtag_instr
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enum jtag_instr
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| Line 697... |
Line 696... |
/* JTAG registers. */
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/* JTAG registers. */
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#define JTAG_MODER (0x0)
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#define JTAG_MODER (0x0)
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#define JTAG_TSEL (0x1)
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#define JTAG_TSEL (0x1)
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#define JTAG_QSEL (0x2)
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#define JTAG_QSEL (0x2)
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#define JTAG_SSEL (0x3)
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#define JTAG_SSEL (0x3)
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#define JTAG_RISCOP (0x9)
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#define JTAG_RISCOP (0x4)
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#define JTAG_RECWP0 (0x10)
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#define JTAG_RECWP0 (0x10)
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#define JTAG_RECBP0 (0x1b)
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#define JTAG_RECBP0 (0x1b)
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/* Current register values. */
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/* Current register values. */
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