| Line 118... |
Line 118... |
#define UPR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 1)
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#define UPR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 1)
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#define CPUCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
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#define CPUCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
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#define DCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 7)
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#define DCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 7)
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#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 16)
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#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 16)
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#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 17)
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#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 17)
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#define PPC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 18)
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#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid))
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#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid))
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#define EPCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 32 + (cid))
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#define EPCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 32 + (cid))
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#define EPCR0_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 32)
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#define EPCR0_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 32)
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#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 0xee)
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#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 0xee)
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| Line 156... |
Line 157... |
/* Defines for SPR bits. */
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/* Defines for SPR bits. */
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#define DMR1_ST (0x00400000)
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#define DMR1_ST (0x00400000)
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/* Changed by CZ 21/06/01 */
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/* Changed by CZ 21/06/01 */
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#define DRR_TE (0x00002000)
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#define DRR_TE (0x00002000)
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#define DRR_BE (0x00001000)
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#define DRR_SSE (0x00001000)
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#define DRR_SCE (0x00000800)
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#define DRR_SCE (0x00000800)
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#define DRR_RE (0x00000400)
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#define DRR_RE (0x00000400)
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#define DRR_IME (0x00000200)
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#define DRR_IME (0x00000200)
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#define DRR_DME (0x00000100)
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#define DRR_DME (0x00000100)
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#define DRR_HPINTE (0x00000080)
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#define DRR_HPINTE (0x00000080)
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| Line 278... |
Line 279... |
This is often the number of bytes in BREAKPOINT
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This is often the number of bytes in BREAKPOINT
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but not always. */
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but not always. */
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#define DECR_PC_AFTER_BREAK 0
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#define DECR_PC_AFTER_BREAK 0
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/* Don't step over l.trap */
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#define CANNOT_STEP_BREAKPOINT
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extern int or1k_insert_breakpoint (CORE_ADDR addr, char *contents_cache);
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extern int or1k_insert_breakpoint (CORE_ADDR addr, char *contents_cache);
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#define target_insert_hw_breakpoint(addr, cache) or1k_insert_breakpoint (addr, cache)
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#define target_insert_hw_breakpoint(addr, cache) or1k_insert_breakpoint (addr, cache)
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extern int or1k_remove_breakpoint (CORE_ADDR addr, char *contents_cache);
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extern int or1k_remove_breakpoint (CORE_ADDR addr, char *contents_cache);
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#define target_remove_hw_breakpoint(addr, cache) or1k_remove_breakpoint (addr, cache)
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#define target_remove_hw_breakpoint(addr, cache) or1k_remove_breakpoint (addr, cache)
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