| Line 41... |
Line 41... |
/* *INDENT-OFF* */
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/* *INDENT-OFF* */
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|
|
/* Group reg name size. See or1k_reg_names. */
|
/* Group reg name size. See or1k_reg_names. */
|
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = {
|
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = {
|
72, 0, 0, 6, 4, 2,
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72, 0, 0, 6, 4, 2,
|
22, 16, 1, 3, 2, 8};
|
22, 16, 1, 3, 2, 8
|
|
};
|
|
|
int or1k_group_name_start[OR1K_NUM_SPR_GROUPS] = {
|
int or1k_group_name_start[OR1K_NUM_SPR_GROUPS] = {
|
0, 0, 0, 253, 254, 256,
|
0, 0, 0, 253, 254, 256,
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0, 248, 16, 16, 255, 0};
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0, 248, 16, 16, 255, 0
|
|
};
|
|
|
/* Generated reg names (max valid alias index).
|
/* Generated reg names (max valid alias index).
|
See or1k_spr_reg_name. */
|
See or1k_spr_reg_name. */
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int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = {
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int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = {
|
2047+1, 2047+1, 2047+1, 258+1, 257+1, 257+1,
|
2047+1, 2047+1, 2047+1, 258+1, 257+1, 257+1,
|
78+1, 263+1, 16+1, 18+1, 256+1, 7+1};
|
78+1, 263+1, 16+1, 18+1, 256+1, 7+1
|
|
};
|
|
|
/* Register names. */
|
/* Register names. */
|
char *or1k_reg_names[] = {
|
char *or1k_reg_names[] = {
|
|
|
/* group 0 - general*/
|
/* group 0 - general*/
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| Line 105... |
Line 108... |
};
|
};
|
|
|
static char *or1k_gdb_reg_names[] = {
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static char *or1k_gdb_reg_names[] = {
|
|
|
/* general purpose registers */
|
/* general purpose registers */
|
"R0", "R1(SP)", "R2(FP)", "R3(A0)", "R4(A1)", "R5(A2)", "R6(A3)", "R7(A4)",
|
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
|
"R8(A5)", "R9(LR)", "R10", "R11(RV)", "R12", "R13", "R14", "R15",
|
"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
|
"R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
|
"R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
|
"R24", "R25", "R26", "R27", "R28", "R29", "R30", "R31",
|
"R24", "R25", "R26", "R27", "R28", "R29", "R30", "R31",
|
|
|
/* Modified by CZ 12/09/01 */
|
/* Modified by CZ 12/09/01 */
|
/* vector/floating point registers */
|
/* vector/floating point registers */
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| Line 120... |
Line 123... |
"VFR24", "VFR25", "VFR26", "VFR27", "VFR28", "VFR29", "VFR30", "VFR31",
|
"VFR24", "VFR25", "VFR26", "VFR27", "VFR28", "VFR29", "VFR30", "VFR31",
|
"PC", "SR", "EPCR", "ExPC", "ExEAR", "ExSR"
|
"PC", "SR", "EPCR", "ExPC", "ExEAR", "ExSR"
|
};
|
};
|
|
|
static char *or1k_group_names[] = {
|
static char *or1k_group_names[] = {
|
"SYS", "DMMU", "IMMU", "DCACHE", "ICACHE", "MAC", "DEBUG", "PERF", "POWER",
|
"SYS", "DMMU", "IMMU", "DCACHE", "ICACHE", "MAC", "DEBUG", "PERF",
|
"PIC", "TIMER", "CONFIG"
|
"POWER", "PIC", "TIMER", "CONFIG"
|
};
|
};
|
|
|
/* Table of or1k signals. */
|
/* Table of or1k signals. */
|
static struct
|
static struct
|
{
|
{
|
| Line 1005... |
Line 1008... |
/* Return adjusted stack pointer. */
|
/* Return adjusted stack pointer. */
|
return sp;
|
return sp;
|
}
|
}
|
|
|
/* Return nonzero when instruction has delay slot. */
|
/* Return nonzero when instruction has delay slot. */
|
|
|
static int
|
static int
|
is_delayed (insn)
|
is_delayed (insn)
|
unsigned long insn;
|
unsigned long insn;
|
{
|
{
|
int i;
|
int index;
|
for (i = 0; i < num_opcodes; ++i)
|
index = insn_decode (insn);
|
if ((or32_opcodes[i].flags & OR32_IF_DELAY)
|
return or32_opcodes[index].flags & OR32_IF_DELAY;
|
&& (or32_opcode_match (insn, or32_opcodes[i].encoding)))
|
|
break;
|
|
return (i < num_opcodes);
|
|
}
|
}
|
|
|
int
|
int
|
or1k_step_skips_delay (pc)
|
or1k_step_skips_delay (pc)
|
CORE_ADDR pc;
|
CORE_ADDR pc;
|
| Line 2252... |
Line 2253... |
int print_insn_little_or32 (bfd_vma,struct disassemble_info*);
|
int print_insn_little_or32 (bfd_vma,struct disassemble_info*);
|
|
|
void
|
void
|
_initialize_or1k_tdep ()
|
_initialize_or1k_tdep ()
|
{
|
{
|
|
build_automata ();
|
/* Added by CZ 26/06/01 */
|
/* Added by CZ 26/06/01 */
|
if(TARGET_BYTE_ORDER == BIG_ENDIAN)
|
if(TARGET_BYTE_ORDER == BIG_ENDIAN)
|
tm_print_insn = print_insn_big_or32;
|
tm_print_insn = print_insn_big_or32;
|
else
|
else
|
tm_print_insn = print_insn_little_or32;
|
tm_print_insn = print_insn_little_or32;
|
| Line 2319... |
Line 2320... |
/* Extra functions supported by simulator. */
|
/* Extra functions supported by simulator. */
|
add_com ("sim", class_obscure, sim_command,
|
add_com ("sim", class_obscure, sim_command,
|
"Send a extended command to the simulator.");
|
"Send a extended command to the simulator.");
|
}
|
}
|
|
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