| Line 284... |
Line 284... |
or1k_write_spr_reg (regno, data)
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or1k_write_spr_reg (regno, data)
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unsigned int regno;
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unsigned int regno;
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unsigned int data;
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unsigned int data;
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{
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{
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or1k_set_chain (SC_RISC_DEBUG);
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or1k_set_chain (SC_RISC_DEBUG);
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or1k_write_reg (regno + REG_SPACE, data);
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or1k_write_reg (regno + REG_SPACE, (ULONGEST)data);
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}
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}
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/* Reads register SPR from regno. */
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/* Reads register SPR from regno. */
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unsigned int
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unsigned int
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| Line 623... |
Line 623... |
if (or1k_status == TARGET_RUNNING)
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if (or1k_status == TARGET_RUNNING)
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error ("Program is already running.");
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error ("Program is already running.");
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else
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else
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error ("The program is not being run.");
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error ("The program is not being run.");
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/* Clear reason register for later. */
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/* Clear reason register for later. */
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or1k_write_spr_reg (DRR_SPRNUM, 0);
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or1k_write_spr_reg (DRR_SPRNUM, 0);
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/* Else clause added by CZ 26/06/01 */
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if (step)
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if (step)
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{
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{
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/* HW STEP. Set DMR1_ST. */
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/* HW STEP. Set DMR1_ST. */
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dmr1 |= DMR1_ST;
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dmr1 |= DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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dmr1 &= ~DMR1_ST;
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dmr1 &= ~DMR1_ST;
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}
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}
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else
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{
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dmr1 &= ~DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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}
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or1k_commit_debug_registers ();
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or1k_commit_debug_registers ();
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/* Run the target. */
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/* Run the target. */
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or1k_unstall ();
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or1k_unstall ();
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or1k_status = TARGET_RUNNING;
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or1k_status = TARGET_RUNNING;
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| Line 717... |
Line 724... |
{
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{
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/* Search all active breakpoints for a match. */
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/* Search all active breakpoints for a match. */
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CORE_ADDR pc = read_pc ();
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CORE_ADDR pc = read_pc ();
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int breakpoint = 0;
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int breakpoint = 0;
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int i;
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int i;
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unsigned long value; /* CZ */
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unsigned char break_bytes[4] = BRK_INSTR_STRUCT;
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unsigned long b_insn = ntohl(*((unsigned long*)break_bytes));
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unsigned long value;
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|
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for (i = 0; i < or1k_implementation.num_used_matchpoints; i++)
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for (i = 0; i < or1k_implementation.num_used_matchpoints; i++)
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if (dvr[i] == pc && dcr[i].dp && dcr[i].cc == CC_EQUAL
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if (dvr[i] == pc && dcr[i].dp && dcr[i].cc == CC_EQUAL
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&& !dcr[i].sc && dcr[i].ct == CT_FETCH)
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&& !dcr[i].sc && dcr[i].ct == CT_FETCH)
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{
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{
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| Line 731... |
Line 740... |
hit_watchpoint = !breakpoint;
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hit_watchpoint = !breakpoint;
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/* Cause the trap/breakpoint exception to be ignored. This is
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/* Cause the trap/breakpoint exception to be ignored. This is
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the behavior of the simulator when the PC value is changed
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the behavior of the simulator when the PC value is changed
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by a write command. All pending exceptions are cleared and
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by a write command. All pending exceptions are cleared and
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the simulator continues at the PC value specified. */
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the simulator continues at the PC value specified. We need
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to do this if the instruction at the current PC has the
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value BRK_INSTR_STRUCT */
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|
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if(b_insn == or1k_read_reg((pc >> 2) + MEM_SPACE))
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{
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or1k_write_spr_reg(PC_SPRNUM,value);
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or1k_write_spr_reg(PC_SPRNUM,value);
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}
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}
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}
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else
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else
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hit_watchpoint = 0;
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hit_watchpoint = 0;
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|
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/* If the stop PC is in the _exit function, assume
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/* If the stop PC is in the _exit function, assume
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we hit the 'break 0x3ff' instruction in _exit, so this
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we hit the 'break 0x3ff' instruction in _exit, so this
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