| Line 43... |
Line 43... |
#define debug if (remote_debug) printf_unfiltered
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#define debug if (remote_debug) printf_unfiltered
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/* The following prototype is necessary or the compiler will not
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/* The following prototype is necessary or the compiler will not
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correctly promote the data argument to ULONGEST */
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correctly promote the data argument to ULONGEST */
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static void or1k_write_reg (unsigned int, ULONGEST);
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static void or1k_write_reg (unsigned int, ULONGEST);
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static int insn_has_delay_slot (unsigned int);
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/* JTAG or1k target ops. */
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/* JTAG or1k target ops. */
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extern void jtag_init PARAMS ((char * args));
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extern void jtag_init PARAMS ((char * args));
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extern ULONGEST jtag_read_reg PARAMS ((unsigned int regno));
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extern ULONGEST jtag_read_reg PARAMS ((unsigned int regno));
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extern void jtag_write_reg PARAMS ((unsigned int regno, ULONGEST data));
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extern void jtag_write_reg PARAMS ((unsigned int regno, ULONGEST data));
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| Line 519... |
Line 520... |
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/* Enable exceptions */
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/* Enable exceptions */
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or1k_write_spr_reg (SR_SPRNUM, or1k_read_spr_reg(SR_SPRNUM) | 0x2);
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or1k_write_spr_reg (SR_SPRNUM, or1k_read_spr_reg(SR_SPRNUM) | 0x2);
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/* Stop when breakpoint occurs. */
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/* Stop when breakpoint occurs. */
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or1k_write_spr_reg (DSR_SPRNUM, 0x2000);
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or1k_write_spr_reg (DSR_SPRNUM, dsr = 0x2000);
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do_cleanups (old_cleanups);
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do_cleanups (old_cleanups);
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/* This should cause an error if not connected. */
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/* This should cause an error if not connected. */
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or1k_fetch_registers (-1);
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or1k_fetch_registers (-1);
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| Line 729... |
Line 730... |
static void
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static void
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or1k_resume (pid, step, siggnal)
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or1k_resume (pid, step, siggnal)
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int pid, step;
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int pid, step;
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enum target_signal siggnal;
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enum target_signal siggnal;
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{
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{
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debug ("pc = %08x\n", read_pc());
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unsigned int pc;
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unsigned int ppc;
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unsigned int npc;
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unsigned int val;
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pc = read_pc();
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npc = or1k_read_spr_reg (PC_SPRNUM);
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ppc = or1k_read_spr_reg (PPC_SPRNUM);
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debug ("pc = %08x BP = %x npc = %08x ppc = %08x\n", pc, breakpoint_here_p (pc), npc, ppc);
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debug ("resume %i, %i, %i\n",step, siggnal, or1k_status);
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debug ("resume %i, %i, %i\n",step, siggnal, or1k_status);
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if (or1k_status != TARGET_STOPPED)
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if (or1k_status != TARGET_STOPPED)
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if (or1k_status == TARGET_RUNNING)
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if (or1k_status == TARGET_RUNNING)
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error ("Program is already running.");
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error ("Program is already running.");
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else
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else
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| Line 750... |
Line 759... |
{
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{
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/* HW STEP. Set DMR1_ST. */
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/* HW STEP. Set DMR1_ST. */
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dmr1 |= DMR1_ST;
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dmr1 |= DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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dmr1 &= ~DMR1_ST;
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dmr1 &= ~DMR1_ST;
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if (breakpoint_here_p (pc) && ((ppc + 4) != npc))
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{
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/* Trapped on delay slot instruction. */
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/* Set PC to branch insn preceding delay slot. */
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or1k_write_spr_reg (PC_SPRNUM, ppc - 4);
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or1k_unstall ();
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or1k_set_chain (SC_REGISTER);
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val = or1k_read_reg (JTAG_RISCOP);
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do {
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val = or1k_read_reg (JTAG_RISCOP);
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} while ((val & 1) == 0);
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}
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else if (breakpoint_here_p (npc) && insn_has_delay_slot (or1k_fetch_instruction (ppc)))
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{
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/* Steping to the trap insn in delay slot - we need to execute branch insn again */
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debug ("resume: steping to the trap insn in delay slot\n");
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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or1k_unstall ();
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or1k_set_chain (SC_REGISTER);
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val = or1k_read_reg (JTAG_RISCOP);
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do {
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val = or1k_read_reg (JTAG_RISCOP);
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} while ((val & 1) == 0);
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}
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else if (breakpoint_here_p (pc))
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or1k_write_spr_reg (PC_SPRNUM, pc);
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}
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}
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else
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else
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{
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{
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dmr1 &= ~DMR1_ST;
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dmr1 &= ~DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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| Line 772... |
Line 812... |
int pid;
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int pid;
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struct target_waitstatus *status;
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struct target_waitstatus *status;
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{
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{
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unsigned long val;
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unsigned long val;
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unsigned long pc;
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unsigned long pc;
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unsigned long npc;
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unsigned long ppc;
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char buf[MAX_REGISTER_RAW_SIZE];
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char buf[MAX_REGISTER_RAW_SIZE];
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interrupt_count = 0;
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interrupt_count = 0;
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debug ("pc = %08x\n", read_pc());
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debug ("wait %i %i\n", pid, or1k_status);
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debug ("wait %i %i\n", pid, or1k_status);
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/* If we have not sent a single step or continue command, then the
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/* If we have not sent a single step or continue command, then the
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board is waiting for us to do something. Return a status
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board is waiting for us to do something. Return a status
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indicating that it is stopped. */
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indicating that it is stopped. */
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if (or1k_status != TARGET_RUNNING)
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if (or1k_status != TARGET_RUNNING)
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| Line 814... |
Line 855... |
drr = or1k_read_spr_reg (DRR_SPRNUM);
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drr = or1k_read_spr_reg (DRR_SPRNUM);
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/* Restore old INT signal handler */
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/* Restore old INT signal handler */
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signal (SIGINT, ofunc);
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signal (SIGINT, ofunc);
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/* If we encounter breakpoint, drr is not set, so we set it manually. */
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/* Single step does not set trap exception, so we set it manually to simplify our code */
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if (!drr)
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dmr1 = or1k_read_spr_reg (DMR1_SPRNUM);
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drr |= DRR_BE;
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if (dmr1 & DMR1_ST)
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drr |= DRR_TE;
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status->kind = TARGET_WAITKIND_STOPPED;
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status->kind = TARGET_WAITKIND_STOPPED;
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debug ("epcr0 = %08x\n", or1k_read_spr_reg (EPCR0_SPRNUM));
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debug ("epcr0 = %08x\n", or1k_read_spr_reg (EPCR0_SPRNUM));
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debug ("drr = %08x\n", drr);
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debug ("drr = %08x\n", drr);
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registers_changed ();
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registers_changed ();
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pc = read_pc ();
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pc = read_pc ();
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debug ("pc = %08x\n", pc);
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npc = or1k_read_spr_reg (PC_SPRNUM);
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ppc = or1k_read_spr_reg (PPC_SPRNUM);
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debug ("npc = %08x ppc = %08x\n", npc, ppc);
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if (drr & DRR_RSTE)
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if (drr & DRR_TE)
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{
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/* If single step is not set, we should correct the pc. */
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if (!(dmr1 & DMR1_ST))
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/* PC has already stepped over the l.trap instruction. */
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pc = ppc;
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status->value.sig = TARGET_SIGNAL_TRAP;
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drr &= ~DRR_TE;
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}
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else if (drr & DRR_RSTE)
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{
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status->value.sig = TARGET_SIGNAL_REALTIME_33;
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status->value.sig = TARGET_SIGNAL_REALTIME_33;
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drr &= ~DRR_RSTE;
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}
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else if (drr & DRR_BUSEE)
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else if (drr & DRR_BUSEE)
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{
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status->value.sig = TARGET_SIGNAL_BUS;
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status->value.sig = TARGET_SIGNAL_BUS;
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else if (drr & DRR_DPFE)
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drr &= ~DRR_BUSEE;
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status->value.sig = TARGET_SIGNAL_REALTIME_34;
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}
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else if (drr & DRR_IPFE)
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status->value.sig = TARGET_SIGNAL_REALTIME_35;
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else if (drr & DRR_LPINTE)
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status->value.sig = TARGET_SIGNAL_INT;
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else if (drr & DRR_AE)
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else if (drr & DRR_AE)
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{
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status->value.sig = TARGET_SIGNAL_REALTIME_36;
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status->value.sig = TARGET_SIGNAL_REALTIME_36;
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drr &= ~DRR_AE;
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}
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else if (drr & DRR_IIE)
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else if (drr & DRR_IIE)
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{
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status->value.sig = TARGET_SIGNAL_ILL;
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status->value.sig = TARGET_SIGNAL_ILL;
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else if (drr & DRR_HPINTE)
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drr &= ~DRR_IIE;
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status->value.sig = TARGET_SIGNAL_INT;
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}
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else if (drr & DRR_DME)
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status->value.sig = TARGET_SIGNAL_REALTIME_37;
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else if (drr & DRR_IME)
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status->value.sig = TARGET_SIGNAL_REALTIME_38;
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else if (drr & DRR_RE)
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else if (drr & DRR_RE)
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{
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status->value.sig = TARGET_SIGNAL_REALTIME_39;
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status->value.sig = TARGET_SIGNAL_REALTIME_39;
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drr &= ~DRR_RE;
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}
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else if (drr & DRR_IME)
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{
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status->value.sig = TARGET_SIGNAL_REALTIME_38;
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drr &= ~DRR_IME;
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}
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else if (drr & DRR_DME)
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{
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status->value.sig = TARGET_SIGNAL_REALTIME_37;
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drr &= ~DRR_DME;
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}
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else if (drr & DRR_DPFE)
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{
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status->value.sig = TARGET_SIGNAL_REALTIME_34;
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drr &= ~DRR_DPFE;
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}
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else if (drr & DRR_IPFE)
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{
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status->value.sig = TARGET_SIGNAL_REALTIME_35;
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drr &= ~DRR_DPFE;
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}
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else if (drr & DRR_SCE)
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else if (drr & DRR_SCE)
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{
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status->value.sig = TARGET_SIGNAL_REALTIME_40;
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status->value.sig = TARGET_SIGNAL_REALTIME_40;
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else if (drr & DRR_BE)
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drr &= ~DRR_SCE;
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status->value.sig = TARGET_SIGNAL_TRAP;
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}
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else if (drr & DRR_TE)
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else if (drr & DRR_HPINTE)
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{
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status->value.sig = TARGET_SIGNAL_INT;
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drr &= ~DRR_HPINTE;
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}
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else if (drr & DRR_LPINTE)
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{
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status->value.sig = TARGET_SIGNAL_INT;
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drr &= ~DRR_LPINTE;
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}
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else
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{
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{
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/* PC has already stepped over the l.trap instruction. */
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pc -= 8;
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status->value.sig = TARGET_SIGNAL_TRAP;
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} else {
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status->value.sig = TARGET_SIGNAL_UNKNOWN;
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status->value.sig = TARGET_SIGNAL_UNKNOWN;
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warning ("Invalid exception occured.");
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warning ("Invalid exception occured.");
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}
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}
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/* Update drr register */
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or1k_write_spr_reg (DRR_SPRNUM, drr);
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/* Write into PC flushes the pipeline! */
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/* Write into PC flushes the pipeline! */
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/* We got the number the register holds, but gdb expects to see a
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/* We got the number the register holds, but gdb expects to see a
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value in the target byte ordering. */
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value in the target byte ordering. */
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write_pc (pc);
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/* write_pc (pc);
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*/
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store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc);
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supply_register (PC_REGNUM, buf);
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/*or1k_write_spr_reg (PC_SPRNUM, pc);
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/*or1k_write_spr_reg (PC_SPRNUM, pc);
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store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc);
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store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc);
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supply_register (PC_REGNUM, buf);*/
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supply_register (PC_REGNUM, buf);*/
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/* Log remote stop. */
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/* Log remote stop. */
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| Line 1660... |
Line 1750... |
if ((dmr2 >> (i + 11)) & 1)
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if ((dmr2 >> (i + 11)) & 1)
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printf_filtered (", increments counter");
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printf_filtered (", increments counter");
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printf_filtered ("\n");
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printf_filtered ("\n");
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}
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}
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}
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}
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static int
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insn_has_delay_slot (insn)
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unsigned int insn;
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{
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if (((insn >> 26) <= 4) || ((insn >> 26) == 17) || ((insn >> 26) == 18))
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return 1;
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else
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return 0;
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}
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void
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void
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_initialize_remote_or1k ()
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_initialize_remote_or1k ()
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{
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{
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/* Initialize the fields in or1k_ops that are common to all targets. */
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/* Initialize the fields in or1k_ops that are common to all targets. */
|
