| Line 164... |
Line 164... |
/* Current register values. */
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/* Current register values. */
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unsigned int dmr1 = 0;
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unsigned int dmr1 = 0;
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unsigned int dmr2 = 0;
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unsigned int dmr2 = 0;
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unsigned int dsr = 0;
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unsigned int dsr = 0;
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unsigned int drr = 0;
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unsigned int drr = 0;
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//unsigned int npc = 0;
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//unsigned int ppc = 0;
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/* Current matchpoints. */
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/* Current matchpoints. */
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unsigned int dvr[MAX_MATCHPOINTS];
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unsigned int dvr[MAX_MATCHPOINTS];
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struct dcr_struct dcr[MAX_MATCHPOINTS];
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struct dcr_struct dcr[MAX_MATCHPOINTS];
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| Line 734... |
Line 736... |
{
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{
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unsigned int pc;
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unsigned int pc;
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unsigned int ppc;
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unsigned int ppc;
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unsigned int npc;
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unsigned int npc;
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unsigned int val;
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unsigned int val;
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int two_steps = 0;
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pc = read_pc();
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pc = read_pc();
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npc = or1k_read_spr_reg (PC_SPRNUM);
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npc = or1k_read_spr_reg (PC_SPRNUM);
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ppc = or1k_read_spr_reg (PPC_SPRNUM);
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ppc = or1k_read_spr_reg (PPC_SPRNUM);
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debug ("pc = %08x BP = %x npc = %08x ppc = %08x\n", pc, breakpoint_here_p (pc), npc, ppc);
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debug ("pc = %08x BP = %x npc = %08x ppc = %08x\n", pc, breakpoint_here_p (pc), npc, ppc);
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| Line 752... |
Line 755... |
/* Clear reason register for later. */
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/* Clear reason register for later. */
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or1k_write_spr_reg (DRR_SPRNUM, 0);
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or1k_write_spr_reg (DRR_SPRNUM, 0);
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or1k_commit_debug_registers ();
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or1k_commit_debug_registers ();
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/* Else clause added by CZ 26/06/01 */
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if (step) {
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if (step)
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/* Always set program counter to branch instruction and reexecute it */
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if (insn_has_delay_slot (or1k_fetch_instruction (ppc)))
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{
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{
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/* HW STEP. Set DMR1_ST. */
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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dmr1 |= DMR1_ST;
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two_steps = 1;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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}
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dmr1 &= ~DMR1_ST;
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else if (breakpoint_here_p (pc) && ((ppc + 4) != npc))
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if (breakpoint_here_p (pc) && ((ppc + 4) != npc))
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{
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{
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/* Trapped on delay slot instruction. */
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/* Trapped on delay slot instruction. */
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/* Set PC to branch insn preceding delay slot. */
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/* Set PC to branch insn preceding delay slot. */
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or1k_write_spr_reg (PC_SPRNUM, ppc - 4);
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or1k_write_spr_reg (PC_SPRNUM, ppc - 4);
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two_steps = 1;
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} else if (breakpoint_here_p (pc))
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or1k_write_spr_reg (PC_SPRNUM, pc);
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or1k_unstall ();
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/* HW STEP. Set DMR1_ST. */
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dmr1 |= DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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dmr1 &= ~DMR1_ST;
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or1k_set_chain (SC_REGISTER);
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if (two_steps)
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val = or1k_read_reg (JTAG_RISCOP);
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do {
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val = or1k_read_reg (JTAG_RISCOP);
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} while ((val & 1) == 0);
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}
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else if (breakpoint_here_p (npc) && insn_has_delay_slot (or1k_fetch_instruction (ppc)))
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{
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{
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/* Steping to the trap insn in delay slot - we need to execute branch insn again */
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debug ("resume: steping to the trap insn in delay slot\n");
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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or1k_unstall ();
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or1k_unstall ();
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or1k_set_chain (SC_REGISTER);
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or1k_set_chain (SC_REGISTER);
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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do {
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do
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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} while ((val & 1) == 0);
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while ((val & 1) == 0);
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}
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}
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else if (breakpoint_here_p (pc))
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or1k_write_spr_reg (PC_SPRNUM, pc);
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}
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}
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else
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else
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{
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{
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dmr1 &= ~DMR1_ST;
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dmr1 &= ~DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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if (breakpoint_here_p (pc))
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or1k_write_spr_reg (PC_SPRNUM, pc);
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}
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}
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/* We can now continue normally, independent of step */
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/* We can now continue normally, independent of step */
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or1k_unstall ();
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or1k_unstall ();
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or1k_status = TARGET_RUNNING;
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or1k_status = TARGET_RUNNING;
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