| Line 159... |
Line 159... |
static int interrupt_count = 0;
|
static int interrupt_count = 0;
|
|
|
/* Reason of last stop. */
|
/* Reason of last stop. */
|
static int hit_watchpoint = 0;
|
static int hit_watchpoint = 0;
|
static int hit_breakpoint = 0;
|
static int hit_breakpoint = 0;
|
static int next_breakpoint = 0;
|
static int new_pc_set = 0;
|
static int prev_step_insn_has_delay_slot = 0;
|
|
|
|
/* Current register values. */
|
/* Current register values. */
|
unsigned int dmr1 = 0;
|
unsigned int dmr1 = 0;
|
unsigned int dmr2 = 0;
|
unsigned int dmr2 = 0;
|
unsigned int dsr = 0;
|
unsigned int dsr = 0;
|
| Line 298... |
Line 297... |
{
|
{
|
or1k_set_chain (SC_RISC_DEBUG);
|
or1k_set_chain (SC_RISC_DEBUG);
|
or1k_write_reg (regno, (ULONGEST)data);
|
or1k_write_reg (regno, (ULONGEST)data);
|
if (regno == PC_SPRNUM) {
|
if (regno == PC_SPRNUM) {
|
hit_breakpoint = 0;
|
hit_breakpoint = 0;
|
prev_step_insn_has_delay_slot = 0;
|
new_pc_set = 1;
|
}
|
}
|
}
|
}
|
|
|
/* Reads register SPR from regno. */
|
/* Reads register SPR from regno. */
|
|
|
| Line 741... |
Line 740... |
{
|
{
|
unsigned int pc;
|
unsigned int pc;
|
unsigned int ppc;
|
unsigned int ppc;
|
unsigned int npc;
|
unsigned int npc;
|
unsigned int val;
|
unsigned int val;
|
|
unsigned int ppc_insn;
|
|
|
pc = read_pc();
|
pc = read_pc();
|
npc = or1k_read_spr_reg (PC_SPRNUM);
|
npc = or1k_read_spr_reg (PC_SPRNUM);
|
ppc = or1k_read_spr_reg (PPC_SPRNUM);
|
ppc = or1k_read_spr_reg (PPC_SPRNUM);
|
debug ("pc = %08x BP = %x npc = %08x ppc = %08x\n", pc, breakpoint_here_p (pc), npc, ppc);
|
debug ("pc = %08x BP = %x npc = %08x ppc = %08x\n", pc, breakpoint_here_p (pc), npc, ppc);
|
| Line 759... |
Line 759... |
/* Clear reason register for later. */
|
/* Clear reason register for later. */
|
or1k_write_spr_reg (DRR_SPRNUM, 0);
|
or1k_write_spr_reg (DRR_SPRNUM, 0);
|
|
|
or1k_commit_debug_registers ();
|
or1k_commit_debug_registers ();
|
|
|
|
ppc_insn = or1k_fetch_instruction(ppc);
|
|
|
/* Else clause added by CZ 26/06/01 */
|
/* Else clause added by CZ 26/06/01 */
|
if (step)
|
if (step)
|
{
|
{
|
/* HW STEP. Set DMR1_ST. */
|
/* HW STEP. Set DMR1_ST. */
|
dmr1 |= DMR1_ST;
|
dmr1 |= DMR1_ST;
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
dmr1 &= ~DMR1_ST;
|
dmr1 &= ~DMR1_ST;
|
|
|
prev_step_insn_has_delay_slot = insn_has_delay_slot (or1k_fetch_instruction (ppc));
|
if (new_pc_set)
|
|
|
if (hit_breakpoint && ((ppc + 4) != npc))
|
|
{
|
{
|
/* Trapped on delay slot instruction. */
|
or1k_write_spr_reg (PC_SPRNUM, pc);
|
/* Set PC to branch insn preceding delay slot. */
|
new_pc_set = 0;
|
or1k_write_spr_reg (PC_SPRNUM, ppc - 4);
|
}
|
|
else if (insn_has_delay_slot (ppc_insn) && (ppc != pc))
|
|
{
|
|
/* Steping across delay slot insn - we have to reexcute branch insn */
|
|
|
|
if(breakpoint_here_p (ppc))
|
|
or1k_write_mem(ppc, ppc_insn);
|
|
|
|
or1k_write_spr_reg (PC_SPRNUM, ppc);
|
|
|
or1k_unstall ();
|
or1k_unstall ();
|
|
|
or1k_set_chain (SC_REGISTER);
|
or1k_set_chain (SC_REGISTER);
|
val = or1k_read_reg (JTAG_RISCOP);
|
val = or1k_read_reg (JTAG_RISCOP);
|
do {
|
do {
|
val = or1k_read_reg (JTAG_RISCOP);
|
val = or1k_read_reg (JTAG_RISCOP);
|
} while ((val & 1) == 0);
|
} while ((val & 1) == 0);
|
}
|
}
|
else if (next_breakpoint && insn_has_delay_slot (or1k_fetch_instruction (ppc)))
|
else if (hit_breakpoint && ((ppc + 4) != npc))
|
{
|
{
|
/* Steping to the trap insn in delay slot - we need to execute branch insn again */
|
/* Trapped on delay slot instruction. */
|
debug ("resume: steping to the trap insn in delay slot\n");
|
/* Set PC to branch insn preceding delay slot. */
|
or1k_write_spr_reg (PC_SPRNUM, ppc);
|
or1k_write_spr_reg (PC_SPRNUM, ppc - 4);
|
|
|
or1k_unstall ();
|
or1k_unstall ();
|
|
|
or1k_set_chain (SC_REGISTER);
|
or1k_set_chain (SC_REGISTER);
|
val = or1k_read_reg (JTAG_RISCOP);
|
val = or1k_read_reg (JTAG_RISCOP);
|
do {
|
do {
|
val = or1k_read_reg (JTAG_RISCOP);
|
val = or1k_read_reg (JTAG_RISCOP);
|
} while ((val & 1) == 0);
|
} while ((val & 1) == 0);
|
}
|
}
|
else if (hit_breakpoint)
|
else
|
or1k_write_spr_reg (PC_SPRNUM, pc);
|
or1k_write_spr_reg (PC_SPRNUM, pc);
|
|
|
}
|
}
|
else
|
else
|
{
|
{
|
dmr1 &= ~DMR1_ST;
|
dmr1 &= ~DMR1_ST;
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
if (prev_step_insn_has_delay_slot)
|
|
|
if (new_pc_set)
|
|
{
|
|
or1k_write_spr_reg (PC_SPRNUM, pc);
|
|
new_pc_set = 0;
|
|
}
|
|
else if (insn_has_delay_slot (ppc_insn) && !breakpoint_here_p (ppc))
|
|
or1k_write_spr_reg (PC_SPRNUM, ppc);
|
|
else if (insn_has_delay_slot (ppc_insn) && breakpoint_here_p (ppc))
|
|
{
|
|
or1k_write_mem(ppc, ppc_insn);
|
|
|
|
dmr1 |= DMR1_ST;
|
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
|
dmr1 &= ~DMR1_ST;
|
|
|
or1k_write_spr_reg (PC_SPRNUM, ppc);
|
or1k_write_spr_reg (PC_SPRNUM, ppc);
|
|
|
|
or1k_unstall ();
|
|
|
|
or1k_set_chain (SC_REGISTER);
|
|
val = or1k_read_reg (JTAG_RISCOP);
|
|
do {
|
|
val = or1k_read_reg (JTAG_RISCOP);
|
|
} while ((val & 1) == 0);
|
|
|
|
or1k_write_mem(ppc, 0x21000001);
|
|
|
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
|
}
|
else
|
else
|
or1k_write_spr_reg (PC_SPRNUM, npc);
|
or1k_write_spr_reg (PC_SPRNUM, pc);
|
}
|
}
|
|
|
/* We can now continue normally, independent of step */
|
/* We can now continue normally, independent of step */
|
or1k_unstall ();
|
or1k_unstall ();
|
or1k_status = TARGET_RUNNING;
|
or1k_status = TARGET_RUNNING;
|
| Line 825... |
Line 862... |
int pid;
|
int pid;
|
struct target_waitstatus *status;
|
struct target_waitstatus *status;
|
{
|
{
|
unsigned long val;
|
unsigned long val;
|
unsigned long pc;
|
unsigned long pc;
|
unsigned long npc;
|
|
unsigned long ppc;
|
unsigned long ppc;
|
char buf[MAX_REGISTER_RAW_SIZE];
|
char buf[MAX_REGISTER_RAW_SIZE];
|
interrupt_count = 0;
|
interrupt_count = 0;
|
|
|
debug ("wait %i %i\n", pid, or1k_status);
|
debug ("wait %i %i\n", pid, or1k_status);
|
| Line 880... |
Line 916... |
debug ("epcr0 = %08x\n", or1k_read_spr_reg (EPCR0_SPRNUM));
|
debug ("epcr0 = %08x\n", or1k_read_spr_reg (EPCR0_SPRNUM));
|
debug ("drr = %08x\n", drr);
|
debug ("drr = %08x\n", drr);
|
|
|
registers_changed ();
|
registers_changed ();
|
pc = read_pc ();
|
pc = read_pc ();
|
npc = or1k_read_spr_reg (PC_SPRNUM);
|
|
ppc = or1k_read_spr_reg (PPC_SPRNUM);
|
ppc = or1k_read_spr_reg (PPC_SPRNUM);
|
debug ("npc = %08x ppc = %08x\n", npc, ppc);
|
debug ("ppc = %08x\n", ppc);
|
|
|
if (drr & DRR_TE)
|
if (drr & DRR_TE)
|
{
|
{
|
/* If single step is not set, we should correct the pc. */
|
/* If single step is not set, we should correct the pc. */
|
if (!(dmr1 & DMR1_ST))
|
if (!(dmr1 & DMR1_ST))
|
| Line 971... |
Line 1006... |
*/
|
*/
|
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc);
|
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc);
|
supply_register (PC_REGNUM, buf);
|
supply_register (PC_REGNUM, buf);
|
|
|
hit_breakpoint = breakpoint_here_p (pc);
|
hit_breakpoint = breakpoint_here_p (pc);
|
next_breakpoint = breakpoint_here_p (npc);
|
|
|
|
/*or1k_write_spr_reg (PC_SPRNUM, pc);
|
/*or1k_write_spr_reg (PC_SPRNUM, pc);
|
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc);
|
store_unsigned_integer (buf, REGISTER_RAW_SIZE (PC_REGNUM), pc);
|
supply_register (PC_REGNUM, buf);*/
|
supply_register (PC_REGNUM, buf);*/
|
|
|
