| Line 187... |
Line 187... |
static void or1k_create_inferior (char *execfile,
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static void or1k_create_inferior (char *execfile,
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char *args,
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char *args,
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char **env,
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char **env,
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int from_tty);
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int from_tty);
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static void or1k_mourn_inferior ();
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static void or1k_mourn_inferior ();
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static void or1k_rcmd (char *command,
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struct ui_file *outbuf);
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/* Global target operations specific to the OR1K */
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/*---------------------------------------------------------------------------*/
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/*!Read a special purpose register from the target
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Use the target operation for this.
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@param[in] regnum The register to read
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@return The value read */
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/*---------------------------------------------------------------------------*/
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ULONGEST
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or1k_read_spr (unsigned int regnum)
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{
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return or1k_jtag_read_spr (regnum);
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} /* or1k_read_spr() */
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/*---------------------------------------------------------------------------*/
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/*!Write a special purpose register on the target
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Use the target operation for this.
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@param[in] regnum The register to write
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@param[in] data The value to write */
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/*---------------------------------------------------------------------------*/
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void
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or1k_write_spr (unsigned int regnum,
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ULONGEST data)
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{
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or1k_jtag_write_spr (regnum, data);
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} /* or1k_write_spr() */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Ask the user about an interrupt
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/*!Ask the user about an interrupt
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| Line 665... |
Line 629... |
}
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}
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/* The "special" registers */
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/* The "special" registers */
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switch (regnum)
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switch (regnum)
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{
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{
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case OR1K_PPC_REGNUM: return OR1K_NPC_SPRNUM;
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case OR1K_NPC_REGNUM: return OR1K_NPC_SPRNUM;
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case OR1K_SR_REGNUM: return OR1K_SR_SPRNUM;
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case OR1K_SR_REGNUM: return OR1K_SR_SPRNUM;
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case OR1K_PC_REGNUM: return OR1K_NPC_SPRNUM;
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default:
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default:
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error ("or1k_regnum_to_sprnum: invalid register number!");
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error ("or1k_regnum_to_sprnum: invalid register number!");
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break;
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break;
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}
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}
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| Line 706... |
Line 671... |
dcr |= or1k_dbgcache.dcr[i].dp ? OR1K_DCR_DP : 0;
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dcr |= or1k_dbgcache.dcr[i].dp ? OR1K_DCR_DP : 0;
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dcr |= (or1k_dbgcache.dcr[i].cc << OR1K_DCR_CC_OFF) & OR1K_DCR_CC;
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dcr |= (or1k_dbgcache.dcr[i].cc << OR1K_DCR_CC_OFF) & OR1K_DCR_CC;
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dcr |= or1k_dbgcache.dcr[i].sc ? OR1K_DCR_SC : 0;
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dcr |= or1k_dbgcache.dcr[i].sc ? OR1K_DCR_SC : 0;
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dcr |= (or1k_dbgcache.dcr[i].ct << OR1K_DCR_CT_OFF) & OR1K_DCR_CT;
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dcr |= (or1k_dbgcache.dcr[i].ct << OR1K_DCR_CT_OFF) & OR1K_DCR_CT;
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or1k_write_spr (OR1K_DVR0_SPRNUM + i, or1k_dbgcache.dvr[i]);
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or1k_jtag_write_spr (OR1K_DVR0_SPRNUM + i, or1k_dbgcache.dvr[i]);
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or1k_write_spr (OR1K_DCR0_SPRNUM + i, dcr);
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or1k_jtag_write_spr (OR1K_DCR0_SPRNUM + i, dcr);
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}
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}
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or1k_write_spr (OR1K_DMR1_SPRNUM, or1k_dbgcache.dmr1);
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or1k_jtag_write_spr (OR1K_DMR1_SPRNUM, or1k_dbgcache.dmr1);
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or1k_write_spr (OR1K_DMR2_SPRNUM, or1k_dbgcache.dmr2);
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or1k_jtag_write_spr (OR1K_DMR2_SPRNUM, or1k_dbgcache.dmr2);
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or1k_write_spr (OR1K_DSR_SPRNUM, or1k_dbgcache.dsr);
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or1k_jtag_write_spr (OR1K_DSR_SPRNUM, or1k_dbgcache.dsr);
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or1k_write_spr (OR1K_DRR_SPRNUM, or1k_dbgcache.drr);
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or1k_jtag_write_spr (OR1K_DRR_SPRNUM, or1k_dbgcache.drr);
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} /* or1k_commit_debug_registers() */
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} /* or1k_commit_debug_registers() */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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| Line 807... |
Line 772... |
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/* Initialize the connection to the remote target. */
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/* Initialize the connection to the remote target. */
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or1k_jtag_init (name);
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or1k_jtag_init (name);
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/* Make sure we have system and debug groups implemented. */
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/* Make sure we have system and debug groups implemented. */
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tmp = or1k_read_spr (OR1K_UPR_SPRNUM);
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tmp = or1k_jtag_read_spr (OR1K_UPR_SPRNUM);
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if (0 == (tmp & OR1K_SPR_UPR_UP))
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if (0 == (tmp & OR1K_SPR_UPR_UP))
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{
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{
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error ("or1k_open: system group missing");
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error ("or1k_open: system group missing");
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}
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}
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if (0 == (tmp & OR1K_SPR_UPR_DUP))
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if (0 == (tmp & OR1K_SPR_UPR_DUP))
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| Line 820... |
Line 785... |
}
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}
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/* Determine number of gpr_regs (this is a bit simplified - the bit just
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/* Determine number of gpr_regs (this is a bit simplified - the bit just
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means "less than 32", but we assume that means 16) and the number of
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means "less than 32", but we assume that means 16) and the number of
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supported watchpoints. */
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supported watchpoints. */
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tmp = or1k_read_spr (OR1K_CPUCFGR_SPRNUM);
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tmp = or1k_jtag_read_spr (OR1K_CPUCFGR_SPRNUM);
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tdep->num_gpr_regs = (0 == (tmp & OR1K_SPR_CPUCFGR_CGF)) ? 32 : 16;
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tdep->num_gpr_regs = (0 == (tmp & OR1K_SPR_CPUCFGR_CGF)) ? 32 : 16;
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tmp = or1k_read_spr (OR1K_DCFGR_SPRNUM);
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tmp = or1k_jtag_read_spr (OR1K_DCFGR_SPRNUM);
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tdep->num_matchpoints = (tmp & OR1K_SPR_DCFGR_NDP) + 1;
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tdep->num_matchpoints = (tmp & OR1K_SPR_DCFGR_NDP) + 1;
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/* Stall the processor. A pause after stalling is appropriate for real
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/* Stall the processor. A pause after stalling is appropriate for real
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hardware. */
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hardware. */
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or1k_jtag_stall ();
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or1k_jtag_stall ();
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| Line 950... |
Line 915... |
{
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{
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error ("or1k_fetch_registers: invalid register number");
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error ("or1k_fetch_registers: invalid register number");
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}
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}
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/* Convert to SPRNUM and read. */
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/* Convert to SPRNUM and read. */
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val = or1k_read_spr (or1k_regnum_to_sprnum (regnum));
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val = or1k_jtag_read_spr (or1k_regnum_to_sprnum (regnum));
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/* We got the number the register holds, but gdb expects to see a value in
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/* We got the number the register holds, but gdb expects to see a value in
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the target byte ordering.
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the target byte ordering.
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This is new for GDB 6.8. Not sure if I need get_thread_regcache() using
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This is new for GDB 6.8. Not sure if I need get_thread_regcache() using
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| Line 996... |
Line 961... |
error ("or1k_store_registers: invalid register number");
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error ("or1k_store_registers: invalid register number");
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}
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}
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regcache = get_current_regcache();
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regcache = get_current_regcache();
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regcache_cooked_read_unsigned (regcache, regnum, &res);
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regcache_cooked_read_unsigned (regcache, regnum, &res);
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or1k_write_spr (or1k_regnum_to_sprnum (regnum), res);
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or1k_jtag_write_spr (or1k_regnum_to_sprnum (regnum), res);
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} /* or1k_store_registers() */
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} /* or1k_store_registers() */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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| Line 1489... |
Line 1454... |
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/* We can now continue normally, independent of step. If this is called for
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/* We can now continue normally, independent of step. If this is called for
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the first time due to a run command, we won't actually be executing, so
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the first time due to a run command, we won't actually be executing, so
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start the target running. */
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start the target running. */
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or1k_write_spr( OR1K_NPC_SPRNUM, read_pc());
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or1k_jtag_write_spr( OR1K_NPC_SPRNUM, read_pc());
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target_has_execution = 1;
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target_has_execution = 1;
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or1k_jtag_unstall ();
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or1k_jtag_unstall ();
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} /* or1k_resume() */
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} /* or1k_resume() */
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| Line 1534... |
Line 1499... |
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/* Registers and frame caches are now all unreliable */
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/* Registers and frame caches are now all unreliable */
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registers_changed();
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registers_changed();
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/* Refresh the debug registers that may have changed */
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/* Refresh the debug registers that may have changed */
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or1k_dbgcache.drr = or1k_read_spr (OR1K_DRR_SPRNUM);
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or1k_dbgcache.drr = or1k_jtag_read_spr (OR1K_DRR_SPRNUM);
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or1k_dbgcache.dmr2 = or1k_read_spr (OR1K_DMR2_SPRNUM);
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or1k_dbgcache.dmr2 = or1k_jtag_read_spr (OR1K_DMR2_SPRNUM);
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/* If we got a trap, then it was a breakpoint/watchpoint of some sort (but
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/* If we got a trap, then it was a breakpoint/watchpoint of some sort (but
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not single step, which does not set the trap exception). We need to back
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not single step, which does not set the trap exception). We need to back
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up the program counter, so the instruction will be re-executed. This
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up the program counter, so the instruction will be re-executed. This
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must be the value of the PPC, in case we have just done a branch. */
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must be the value of the PPC, in case we have just done a branch. */
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if (OR1K_DRR_TE == (or1k_dbgcache.drr & OR1K_DRR_TE))
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if (OR1K_DRR_TE == (or1k_dbgcache.drr & OR1K_DRR_TE))
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{
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{
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write_pc (or1k_read_spr (OR1K_PPC_SPRNUM));
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write_pc (or1k_jtag_read_spr (OR1K_PPC_SPRNUM));
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}
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}
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/* Single step does not set trap exception, so we set it manually to
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/* Single step does not set trap exception, so we set it manually to
|
simplify our code. */
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simplify our code. */
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if (OR1K_DMR1_ST == (or1k_dbgcache.dmr1 & OR1K_DMR1_ST))
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if (OR1K_DMR1_ST == (or1k_dbgcache.dmr1 & OR1K_DMR1_ST))
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| Line 1583... |
Line 1548... |
interrupt. This happens at reset and exit. The latter we distinquish
|
interrupt. This happens at reset and exit. The latter we distinquish
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by looking at the instruction just executed, to see if it is
|
by looking at the instruction just executed, to see if it is
|
"l.nop NOP_EXIT". If this is the case, get the result from GPR 3 and
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"l.nop NOP_EXIT". If this is the case, get the result from GPR 3 and
|
set the NPC to the reset vector, so a new start will behave well. */
|
set the NPC to the reset vector, so a new start will behave well. */
|
|
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addr = or1k_read_spr (OR1K_PPC_SPRNUM);
|
addr = or1k_jtag_read_spr (OR1K_PPC_SPRNUM);
|
res = read_memory_nobpt (addr, buf, OR1K_INSTLEN);
|
res = read_memory_nobpt (addr, buf, OR1K_INSTLEN);
|
if (0 != res)
|
if (0 != res)
|
{
|
{
|
memory_error (res, addr);
|
memory_error (res, addr);
|
}
|
}
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| Line 1721... |
Line 1686... |
}
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}
|
} /* or1k_mourn_inferior () */
|
} /* or1k_mourn_inferior () */
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|
|
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/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
|
/*!Send a command to the remote target
|
|
|
|
The target can't actually run any remote commands, in the sense of having a
|
|
command interpreter. However we use this as a GDB "standard" way of
|
|
wrapping up commands to access the SPRs.
|
|
|
|
Current commands supported are:
|
|
- readspr <regno>
|
|
- writespr <regno> <value>
|
|
|
|
The output is either the value read (for successful read) or OK (for
|
|
successful write) or E01 to indicate and wrror. All values are represented
|
|
as unsigned hex.
|
|
|
|
@param[in] command The command to execute
|
|
@param[out] output The result of the command */
|
|
/*---------------------------------------------------------------------------*/
|
|
|
|
static void or1k_rcmd (char *command,
|
|
struct ui_file *outbuf)
|
|
{
|
|
/* Sort out which command */
|
|
if (0 == strncmp ("readspr", command, strlen ("readspr")))
|
|
{
|
|
unsigned int regno; /* SPR to read */
|
|
|
|
if (1 != sscanf (command, "readspr %4x", ®no))
|
|
{
|
|
error ("or1k_rcmd: unrecognized readspr");
|
|
fputs_unfiltered ("E01", outbuf);
|
|
}
|
|
else
|
|
{
|
|
char strbuf[sizeof ("ffffffff")];
|
|
ULONGEST data = or1k_jtag_read_spr (regno);
|
|
|
|
sprintf (strbuf, "%8llx", data);
|
|
fputs_unfiltered (strbuf, outbuf);
|
|
}
|
|
}
|
|
else if (0 == strncmp ("writespr", command, strlen ("writespr")))
|
|
{
|
|
unsigned int regno; /* SPR to write */
|
|
ULONGEST data; /* Value to write */
|
|
|
|
if (2 != sscanf (command, "writespr %4x %8llx", ®no, &data))
|
|
{
|
|
error ("or1k_rcmd: unrecognized writespr");
|
|
fputs_unfiltered ("E01", outbuf);
|
|
}
|
|
else
|
|
{
|
|
or1k_jtag_write_spr (regno, data);
|
|
fputs_unfiltered ("OK", outbuf);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
error ("or1k_rcmd: unrecognized remote command");
|
|
fputs_unfiltered ("E01", outbuf);
|
|
}
|
|
} /* or1k_rcmd () */
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*!Main entry point for the remote OpenRISC JTAG protocol
|
/*!Main entry point for the remote OpenRISC JTAG protocol
|
|
|
Initializes the target ops for each version of the remote
|
Initializes the target ops for each version of the remote
|
protocol. Currently only the JTAG protocol is implemented.
|
protocol. Currently only the JTAG protocol is implemented.
|
|
|
| Line 1790... |
Line 1820... |
or1k_target.to_stop = or1k_stop;
|
or1k_target.to_stop = or1k_stop;
|
or1k_target.to_kill = or1k_kill;
|
or1k_target.to_kill = or1k_kill;
|
or1k_target.to_create_inferior = or1k_create_inferior;
|
or1k_target.to_create_inferior = or1k_create_inferior;
|
or1k_target.to_mourn_inferior = or1k_mourn_inferior;
|
or1k_target.to_mourn_inferior = or1k_mourn_inferior;
|
|
|
|
or1k_target.to_rcmd = or1k_rcmd;
|
|
|
or1k_target.to_magic = OPS_MAGIC;
|
or1k_target.to_magic = OPS_MAGIC;
|
|
|
/* Tell GDB about the new target */
|
/* Tell GDB about the new target */
|
|
|
add_target (&or1k_target);
|
add_target (&or1k_target);
|
