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/* Information about OR1K ISA. W/o this we can't generate or1k_isa_part.tex.
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/* Information about OR1K ISA. W/o this we can't generate or1k_isa_part.tex.
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*
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*
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.11 2003/01/28 03:43:04 lampret
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* Typos by Maria Bolado
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*
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*/
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*/
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struct or1k_isa {
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struct or1k_isa {
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char *name;
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char *name;
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char *title;
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char *title;
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| Line 29... |
Line 32... |
{
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{
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/*** ORBIS32 ***/
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/*** ORBIS32 ***/
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|
|
{"l.addi", "Add Immediate Signed",
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{"l.addi", "Add Immediate Signed",
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"The immediate value is signed-extended and added to the contents of general-purpose"
|
"The immediate value is sign-extended and added to the contents of general-purpose"
|
"register rA to form the result. The result is placed into general-purpose"
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"register rA to form the result. The result is placed into general-purpose"
|
"register rD.",
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"register rD.",
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"rD[31:0] <- rA[31:0] + exts(Immediate)\\SR[CY] <- carry\\SR[OV] <- overflow",
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"rD[31:0] <- rA[31:0] + exts(Immediate)\\SR[CY] <- carry\\SR[OV] <- overflow",
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"rD[63:0] <- rA[63:0] + exts(Immediate)\\SR[CY] <- carry\\SR[OV] <- overflow",
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"rD[63:0] <- rA[63:0] + exts(Immediate)\\SR[CY] <- carry\\SR[OV] <- overflow",
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"Range Exception", ORBIS32I,},
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"Range Exception", ORBIS32I,},
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|
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{"l.addic", "Add Immediate Signed and Carry",
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"The immediate value is sign-extended and added to the contents of general-purpose"
|
|
"register rA and carry SR[CY] to form the result. "
|
|
"The result is placed into general-purpose register rD.",
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"rD[31:0] <- rA[31:0] + exts(Immediate) + SR[CY]\\SR[CY] <- carry\\SR[OV] <- overflow",
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"rD[63:0] <- rA[63:0] + exts(Immediate) + SR[CY]\\SR[CY] <- carry\\SR[OV] <- overflow",
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"Range Exception", ORBIS32I,},
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{"l.andi", "And with Immediate Half Word",
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{"l.andi", "And with Immediate Half Word",
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"The immediate value is zero-extended and combined with the contents "
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"The immediate value is zero-extended and combined with the contents "
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"of general-purpose register rA in a bit-wise logical AND operation. The "
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"of general-purpose register rA in a bit-wise logical AND operation. The "
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"result is placed into general-purpose register rD.",
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"result is placed into general-purpose register rD.",
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"rD[31:0] <- rA[31:0] AND extz(Immediate)",
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"rD[31:0] <- rA[31:0] AND extz(Immediate)",
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| Line 53... |
Line 64... |
"rD[31:0] <- rA[31:0] OR extz(Immediate)",
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"rD[31:0] <- rA[31:0] OR extz(Immediate)",
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"rD[63:0] <- rA[63:0] OR extz(Immediate)",
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"rD[63:0] <- rA[63:0] OR extz(Immediate)",
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"None", ORBIS32I,},
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"None", ORBIS32I,},
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|
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{"l.xori", "Exclusive Or with Immediate Half Word",
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{"l.xori", "Exclusive Or with Immediate Half Word",
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"The immediate value is zero-extended and combined with the contents of general-purpose "
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"The immediate value is sign-extended and combined with the contents of general-purpose "
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"register rA in a bit-wise logical XOR operation. The result is "
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"register rA in a bit-wise logical XOR operation. The result is "
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"placed into general-purpose register rD.",
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"placed into general-purpose register rD.",
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"rD[31:0] <- rA[31:0] XOR extz(Immediate)",
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"rD[31:0] <- rA[31:0] XOR exts(Immediate)",
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"rD[63:0] <- rA[63:0] XOR extz(Immediate)",
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"rD[63:0] <- rA[63:0] XOR exts(Immediate)",
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"None", ORBIS32I,},
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"None", ORBIS32I,},
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|
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{"l.slli", "Shift Left Logical with Immediate",
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{"l.slli", "Shift Left Logical with Immediate",
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"The 6-bit immediate value specifies the number of "
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"The immediate value specifies the number of "
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"bit positions; the contents of general-purpose register rA are shifted left, "
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"bit positions; the contents of general-purpose register rA are shifted left, "
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"inserting zeros into the low-order bits. The result is written into general-purpose "
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"inserting zeros into the low-order bits. The result is written into general-purpose "
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"register rD.",
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"register rD. In 32-bit implementations bit 5 of immediate is ignored.",
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"rD[31:L] <- rA[31-L:0]\\rD[L-1:0] <- 0",
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"rD[31:L] <- rA[31-L:0]\\rD[L-1:0] <- 0",
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"rD[63:L] <- rA[63-L:0]\\rD[L-1:0] <- 0",
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"rD[63:L] <- rA[63-L:0]\\rD[L-1:0] <- 0",
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"None", ORBIS32I,},
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"None", ORBIS32I,},
|
|
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{"l.srai", "Shift Right Arithmetic with Immediate",
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{"l.srai", "Shift Right Arithmetic with Immediate",
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"The 6-bit immediate value specifies the number of "
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"The 6-bit immediate value specifies the number of "
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"bit positions; the contents of general-purpose register rA are shifted right, "
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"bit positions; the contents of general-purpose register rA are shifted right, "
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"sign-extending the high-order bits. The result is written into "
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"sign-extending the high-order bits. The result is written into "
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"general-purpose register rD.",
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"general-purpose register rD. In 32-bit implementations bit 5 of immediate is ignored.",
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"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- \{rA[31]\}",
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"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- \{rA[31]\}",
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"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- \{rA[63]\}",
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"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- \{rA[63]\}",
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"None", ORBIS32I,},
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"None", ORBIS32I,},
|
|
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{"l.srli", "Shift Right Logical with Immediate",
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{"l.srli", "Shift Right Logical with Immediate",
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"The 6-bit immediate value specifies the number of "
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"The 6-bit immediate value specifies the number of "
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"bit positions; the contents of general-purpose register rA are shifted right, "
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"bit positions; the contents of general-purpose register rA are shifted right, "
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"inserting zeros into the high-order bits. The result is written into general-purpose "
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"inserting zeros into the high-order bits. The result is written into general-purpose "
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"register rD.",
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"register rD. In 32-bit implementations bit 5 of immediate is ignored.",
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"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- 0",
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"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- 0",
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"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- 0",
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"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- 0",
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"None", ORBIS32I,},
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"None", ORBIS32I,},
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|
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{"l.rori", "Rotate Right with Immediate",
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{"l.rori", "Rotate Right with Immediate",
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"The 6-bit immediate value specifies the number of "
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"The 6-bit immediate value specifies the number of "
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"bit positions; the contents of general-purpose register rA are rotated right. "
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"bit positions; the contents of general-purpose register rA are rotated right. "
|
"The result is written into general-purpose register rD.",
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"The result is written into general-purpose register rD. In 32-bit implementations bit 5 of immediate is ignored.",
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"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- rA[L-1:0]",
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"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- rA[L-1:0]",
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"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- rA[L-1:0]",
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"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- rA[L-1:0]",
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"None", ORBIS32I,},
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"None", ORBIS32I,},
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{"l.muli", "Multiply Immediate Signed",
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{"l.muli", "Multiply Immediate Signed",
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| Line 185... |
Line 196... |
"general-purpose register rD. "
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"general-purpose register rD. "
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"High-order bits of general-purpose register rD are replaced with "
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"High-order bits of general-purpose register rD are replaced with "
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"bit 7 of the loaded value.",
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"bit 7 of the loaded value.",
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"EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- (EA)[7]",
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"EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- (EA)[7]",
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"EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- (EA)[7]",
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"EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- (EA)[7]",
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"TLB miss\\Page fault\\Bus error\\Alignment", ORBIS32I,},
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"TLB miss\\Page fault\\Bus error", ORBIS32I,},
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{"l.lhs", "Load Half Word and Extend with Sign",
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{"l.lhs", "Load Half Word and Extend with Sign",
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"The offset is sign-extended and added to the contents of general-purpose "
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"The offset is sign-extended and added to the contents of general-purpose "
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"register rA. The sum represents an effective address. The half word in memory "
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"register rA. The sum represents an effective address. The half word in memory "
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"addressed by EA is loaded into the low-order 16 bits of "
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"addressed by EA is loaded into the low-order 16 bits of "
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Line 229... |
"general-purpose register rD. "
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"general-purpose register rD. "
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"High-order bits of general-purpose register rD are replaced with "
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"High-order bits of general-purpose register rD are replaced with "
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"zero.",
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"zero.",
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"EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- 0",
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"EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- 0",
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"EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- 0",
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"EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- 0",
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"TLB miss\\Page fault\\Bus error\\Alignment", ORBIS32I,},
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"TLB miss\\Page fault\\Bus error", ORBIS32I,},
|
|
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{"l.lhz", "Load Half Word and Extend with Zero",
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{"l.lhz", "Load Half Word and Extend with Zero",
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"The offset is sign-extended and added to the contents of general-purpose "
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"The offset is sign-extended and added to the contents of general-purpose "
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"register rA. The sum represents an effective address. The half word in memory "
|
"register rA. The sum represents an effective address. The half word in memory "
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"addressed by EA is loaded into the low-order 16 bits of "
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"addressed by EA is loaded into the low-order 16 bits of "
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| Line 280... |
Line 291... |
"The offset is sign-extended and added to the contents of general-purpose "
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"The offset is sign-extended and added to the contents of general-purpose "
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"register rA. The sum represents an effective address. The low-order 8 bits "
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"register rA. The sum represents an effective address. The low-order 8 bits "
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"of general-purpose register rB are stored to memory location addressed by EA. ",
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"of general-purpose register rB are stored to memory location addressed by EA. ",
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"EA <- exts(Immediate) + rA[31:0]\\(EA)[7:0] <- rB[7:0]",
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"EA <- exts(Immediate) + rA[31:0]\\(EA)[7:0] <- rB[7:0]",
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"EA <- exts(Immediate) + rA[63:0]\\(EA)[7:0] <- rB[7:0]",
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"EA <- exts(Immediate) + rA[63:0]\\(EA)[7:0] <- rB[7:0]",
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"TLB miss\\Page fault\\Bus error\\Alignment", ORBIS32I,},
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"TLB miss\\Page fault\\Bus error", ORBIS32I,},
|
|
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{"l.add", "Add Signed",
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{"l.add", "Add Signed",
|
"The contents of general-purpose register rA are added to the contents "
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"The contents of general-purpose register rA are added to the contents "
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"of general-purpose register rB to form the result. The result is placed into "
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"of general-purpose register rB to form the result. The result is placed into "
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"general-purpose register rD.",
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"general-purpose register rD.",
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| Line 301... |
Line 312... |
"Range Exception", ORBIS32I,},
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"Range Exception", ORBIS32I,},
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|
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{"l.sub", "Subtract Signed",
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{"l.sub", "Subtract Signed",
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"The contents of general-purpose register rB are subtracted from the contents "
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"The contents of general-purpose register rB are subtracted from the contents "
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"of general-purpose register rA to form the result. The result is placed into "
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"of general-purpose register rA to form the result. The result is placed into "
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"general-purpose register rD.",
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"general-purpose register rD. This isntruction does not change carry SR[CY] flag.",
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"rD[31:0] <- rA[31:0] - rB[31:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
|
"rD[31:0] <- rA[31:0] - rB[31:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
|
"rD[63:0] <- rA[63:0] - rB[63:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
|
"rD[63:0] <- rA[63:0] - rB[63:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
|
"Range Exception", ORBIS32I,},
|
"Range Exception", ORBIS32I,},
|
|
|
{"l.sll", "Shift Left Logical",
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{"l.sll", "Shift Left Logical",
|
"General-purpose register rB specifies the number of "
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"General-purpose register rB specifies the number of "
|
"bit positions; the contents of general-purpose register rA are shifted left, "
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"bit positions; the contents of general-purpose register rA are shifted left, "
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"inserting zeros into the low-order bits. The result is written into general-purpose "
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"inserting zeros into the low-order bits. The result is written into general-purpose "
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"rD.",
|
"rD. In 32-bit implementations bit 5 of rB is ignored.",
|
"rD[31:rB[5:0]] <- rA[31-rB[5:0]:0]\\rD[rB[5:0]-1:0] <- 0",
|
"rD[31:rB[4:0]] <- rA[31-rB[4:0]:0]\\rD[rB[4:0]-1:0] <- 0",
|
"rD[63:rB[5:0]] <- rA[63-rB[5:0]:0]\\rD[rB[5:0]-1:0] <- 0",
|
"rD[63:rB[5:0]] <- rA[63-rB[5:0]:0]\\rD[rB[5:0]-1:0] <- 0",
|
"None", ORBIS32I,},
|
"None", ORBIS32I,},
|
|
|
{"l.sra", "Shift Right Arithmetic",
|
{"l.sra", "Shift Right Arithmetic",
|
"General-purpose register rB specifies the number of "
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"General-purpose register rB specifies the number of "
|
"bit positions; the contents of general-purpose register rA are shifted right, "
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"bit positions; the contents of general-purpose register rA are shifted right, "
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"sign-extending the high-order bits. The result is written into "
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"sign-extending the high-order bits. The result is written into "
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"general-purpose register rD.",
|
"general-purpose register rD. In 32-bit implementations bit 5 of rB is ignored.",
|
"rD[31-rB[5:0]:0] <- rA[31:rB[5:0]]\\rD[31:32-rB[5:0]] <- \{rA[31]\}",
|
"rD[31-rB[4:0]:0] <- rA[31:rB[4:0]]\\rD[31:32-rB[4:0]] <- \{rA[31]\}",
|
"rD[63-rB[5:0]:0] <- rA[63:rB[5:0]]\\rD[63:64-rB[5:0]] <- \{rA[63]\}",
|
"rD[63-rB[5:0]:0] <- rA[63:rB[5:0]]\\rD[63:64-rB[5:0]] <- \{rA[63]\}",
|
"None", ORBIS32I,},
|
"None", ORBIS32I,},
|
|
|
{"l.srl", "Shift Right Logical",
|
{"l.srl", "Shift Right Logical",
|
"General-purpose register rB specifies the number of "
|
"General-purpose register rB specifies the number of "
|
"bit positions; the contents of general-purpose register rA are shifted right, "
|
"bit positions; the contents of general-purpose register rA are shifted right, "
|
"inserting zeros into the high-order bits. The result is written into general-purpose "
|
"inserting zeros into the high-order bits. The result is written into general-purpose "
|
"register rD.",
|
"register rD. In 32-bit implementations bit 5 of rB is ignored.",
|
"rD[31-rB[5:0]:0] <- rA[31:rB[5:0]]\\rD[31:32-rB[5:0]] <- 0",
|
"rD[31-rB[4:0]:0] <- rA[31:rB[4:0]]\\rD[31:32-rB[4:0]] <- 0",
|
"rD[63-rB[5:0]:0] <- rA[63:rB[5:0]]\\rD[63:64-rB[5:0]] <- 0",
|
"rD[63-rB[5:0]:0] <- rA[63:rB[5:0]]\\rD[63:64-rB[5:0]] <- 0",
|
"None", ORBIS32I,},
|
"None", ORBIS32I,},
|
|
|
{"l.ror", "Rotate Right",
|
{"l.ror", "Rotate Right",
|
"General-purpose register rB specifies the number of "
|
"General-purpose register rB specifies the number of "
|
"bit positions; the contents of general-purpose register rA are rotated right. "
|
"bit positions; the contents of general-purpose register rA are rotated right. "
|
"The result is written into general-purpose register rD.",
|
"The result is written into general-purpose register rD. In 32-bit implementations bit 5 of rB is ignored.",
|
"rD[31-rB[5:0]:0] <- rA[31:rB]\\rD[31:32-rB[5:0]] <- rA[rB[5:0]-1:0]",
|
"rD[31-rB[4:0]:0] <- rA[31:rB]\\rD[31:32-rB[4:0]] <- rA[rB[4:0]-1:0]",
|
"rD[63-rB[5:0]:0] <- rA[63:rB]\\rD[63:64-rB[5:0]] <- rA[rB[5:0]-1:0]",
|
"rD[63-rB[5:0]:0] <- rA[63:rB]\\rD[63:64-rB[5:0]] <- rA[rB[5:0]-1:0]",
|
"None", ORBIS32II,},
|
"None", ORBIS32II,},
|
|
|
{"l.and", "And",
|
{"l.and", "And",
|
"The contents of general-purpose register rA are combined with the contents "
|
"The contents of general-purpose register rA are combined with the contents "
|
| Line 379... |
Line 390... |
{"l.maci0", "Multiply Immediate Signed",
|
{"l.maci0", "Multiply Immediate Signed",
|
"The immediate value and the contents of general-purpose register rA are "
|
"The immediate value and the contents of general-purpose register rA are "
|
"multiplied, and the result is truncated to 32 bits and stored "
|
"multiplied, and the result is truncated to 32 bits and stored "
|
"into the special-purpose registers MACHI and MACLO. "
|
"into the special-purpose registers MACHI and MACLO. "
|
"All operands are treated as signed integers.",
|
"All operands are treated as signed integers.",
|
"temp[31:0] <- rA[31:0] * Immediate\\MACHI[31:0]MACLO[31:0] <- temp[31:0]\\",
|
"temp[31:0] <- rA[31:0] * exts(Immediate)\\MACHI[31:0]MACLO[31:0] <- temp[31:0]\\",
|
"temp[31:0] <- rA[63:0] * Immediate\\MACHI[31:0]MACLO[31:0] <- temp[31:0]\\",
|
"temp[31:0] <- rA[63:0] * exts(Immediate)\\MACHI[31:0]MACLO[31:0] <- temp[31:0]\\",
|
"None", ORBIS32II,},
|
"None", ORBIS32II,},
|
|
|
{"l.mac", "Multiply Signed and Accumulate",
|
{"l.mac", "Multiply Signed and Accumulate",
|
"The contents of general-purpose register rA and the contents of general-purpose "
|
"The contents of general-purpose register rA and the contents of general-purpose "
|
"register rB are multiplied, and the result is truncated to 32 bits and added "
|
"register rB are multiplied, and the result is truncated to 32 bits and added "
|
| Line 392... |
Line 403... |
"All operands are treated as signed integers.",
|
"All operands are treated as signed integers.",
|
"temp[31:0] <- rA[31:0] * rB[31:0]\\MACHI[31:0]MACLO[31:0] <- temp[31:0] + MACHI[31:0]MACLO[31:0]\\",
|
"temp[31:0] <- rA[31:0] * rB[31:0]\\MACHI[31:0]MACLO[31:0] <- temp[31:0] + MACHI[31:0]MACLO[31:0]\\",
|
"temp[31:0] <- rA[63:0] * rB[63:0]\\MACHI[31:0]MACLO[31:0] <- temp[31:0] + MACHI[31:0]MACLO[31:0]\\",
|
"temp[31:0] <- rA[63:0] * rB[63:0]\\MACHI[31:0]MACLO[31:0] <- temp[31:0] + MACHI[31:0]MACLO[31:0]\\",
|
"None", ORBIS32II,},
|
"None", ORBIS32II,},
|
|
|
|
{"l.msb", "Multiply Signed and Subtract",
|
|
"The contents of general-purpose register rA and the contents of general-purpose "
|
|
"register rB are multiplied, and the result is truncated to 32 bits and subtracted "
|
|
"from the special-purpose registers MACHI and MACLO. Result of the subtraction is "
|
|
"placed into MACHI and MACLO registers."
|
|
"All operands are treated as signed integers.",
|
|
"temp[31:0] <- rA[31:0] * rB[31:0]\\MACHI[31:0]MACLO[31:0] <- MACHI[31:0]MACLO[31:0] - temp[31:0]\\",
|
|
"temp[31:0] <- rA[63:0] * rB[63:0]\\MACHI[31:0]MACLO[31:0] <- MACHI[31:0]MACLO[31:0] - temp[31:0]\\",
|
|
"None", ORBIS32II,},
|
|
|
{"l.maci", "Multiply Immediate Signed and Accumulate",
|
{"l.maci", "Multiply Immediate Signed and Accumulate",
|
"The immediate value and the contents of general-purpose register rA are "
|
"The immediate value and the contents of general-purpose register rA are "
|
"multiplied, and the result is truncated to 32 bits and added "
|
"multiplied, and the result is truncated to 32 bits and added "
|
"to the special-purpose registers MACHI and MACLO. "
|
"to the special-purpose registers MACHI and MACLO. "
|
"All operands are treated as signed integers.",
|
"All operands are treated as signed integers.",
|
"temp[31:0] <- rA[31:0] * Immediate\\MACHI[31:0]MACLO[31:0] <- temp[31:0] + MACHI[31:0]MACLO[31:0]\\",
|
"temp[31:0] <- rA[31:0] * exts(Immediate)\\MACHI[31:0]MACLO[31:0] <- temp[31:0] + MACHI[31:0]MACLO[31:0]\\",
|
"temp[31:0] <- rA[63:0] * Immediate\\MACHI[31:0]MACLO[31:0] <- temp[31:0] + MACHI[31:0]MACLO[31:0]\\",
|
"temp[31:0] <- rA[63:0] * exts(Immediate)\\MACHI[31:0]MACLO[31:0] <- temp[31:0] + MACHI[31:0]MACLO[31:0]\\",
|
"None", ORBIS32II,},
|
"None", ORBIS32II,},
|
|
|
{"l.macr", "Read And Synchronize MAC",
|
{"l.macrc", "MAC Read and Clear",
|
"Once all instructions in MAC pipeline are completed, the contents of MAC is stored in "
|
"Once all instructions in MAC pipeline are completed, the contents of MAC is placed into "
|
"general-purpose register rD.",
|
"general-purpose register rD and MAC accumulator is cleared.",
|
"synchronize-mac\\"
|
"synchronize-mac\\"
|
"rD[31:0] <- MACLO[31:0]\\",
|
"rD[31:0] <- MACLO[31:0]\\"
|
|
"MACHI[31:0]MACLO[31:0] <- 0\\",
|
"synchronize-mac\\"
|
"synchronize-mac\\"
|
"rD[63:0] <- MACHI[31:0]MACLO[31:0]\\",
|
"rD[63:0] <- MACHI[31:0]MACLO[31:0]\\"
|
|
"MACHI[31:0]MACLO[31:0] <- 0\\",
|
"None", ORBIS32II,},
|
"None", ORBIS32II,},
|
|
|
{"l.mul", "Multiply Signed",
|
{"l.mul", "Multiply Signed",
|
"The contents of general-purpose register rA and the contents of general-purpose "
|
"The contents of general-purpose register rA and the contents of general-purpose "
|
"register rB are multiplied, and the result is truncated to destination register width "
|
"register rB are multiplied, and the result is truncated to destination register width "
|
| Line 432... |
Line 455... |
|
|
{"l.div", "Divide Signed",
|
{"l.div", "Divide Signed",
|
"The content of general-purpose register rA are divided by the content of "
|
"The content of general-purpose register rA are divided by the content of "
|
"general-purpose register rB, and the result is placed into general-purpose register "
|
"general-purpose register rB, and the result is placed into general-purpose register "
|
"rD. Both operands are treated as signed integers. A carry "
|
"rD. Both operands are treated as signed integers. A carry "
|
"flag is set when the divisor is zero.",
|
"flag is set when the divisor is zero (if carry SR[CY] is implemented).",
|
"rD[31:0] <- rA[31:0] / rB[31:0]\\SR[OV] <- overflow\\SR[CY] <- carry",
|
"rD[31:0] <- rA[31:0] / rB[31:0]\\SR[OV] <- overflow\\SR[CY] <- carry",
|
"rD[63:0] <- rA[63:0] / rB[63:0]\\SR[OV] <- overflow\\SR[CY] <- carry",
|
"rD[63:0] <- rA[63:0] / rB[63:0]\\SR[OV] <- overflow\\SR[CY] <- carry",
|
"Range Exception", ORBIS32II,},
|
"Range Exception", ORBIS32II,},
|
|
|
{"l.divu", "Divide Unsigned",
|
{"l.divu", "Divide Unsigned",
|
"The content of general-purpose register rA are divided by the content of "
|
"The content of general-purpose register rA are divided by the content of "
|
"general-purpose register rA, and the result is placed into general-purpose register "
|
"general-purpose register rB, and the result is placed into general-purpose register "
|
"rD. Both operands are treated as unsigned integers. A carry "
|
"rD. Both operands are treated as unsigned integers. A carry "
|
"flag is set when the divisor is zero.",
|
"flag is set when the divisor is zero (if carry SR[CY] is implemented).",
|
"rD[31:0] <- rA[31:0] / rB[31:0]\\SR[OV] <- overflow\\SR[CY] <- carry",
|
"rD[31:0] <- rA[31:0] / rB[31:0]\\SR[OV] <- overflow\\SR[CY] <- carry",
|
"rD[63:0] <- rA[63:0] / rB[63:0]\\SR[OV] <- overflow\\SR[CY] <- carry",
|
"rD[63:0] <- rA[63:0] / rB[63:0]\\SR[OV] <- overflow\\SR[CY] <- carry",
|
"Range Exception", ORBIS32II,},
|
"Range Exception", ORBIS32II,},
|
|
|
{"l.sfeq", "Set Flag if Equal",
|
{"l.sfeq", "Set Flag if Equal",
|
| Line 632... |
Line 655... |
"SR[F] <- rA[63:0] <= extz(Immediate)",
|
"SR[F] <- rA[63:0] <= extz(Immediate)",
|
"None", ORBIS32II,},
|
"None", ORBIS32II,},
|
|
|
{"l.mtspr", "Move To Special-Purpose Register",
|
{"l.mtspr", "Move To Special-Purpose Register",
|
"The contents of general-purpose register rB are moved into the special register "
|
"The contents of general-purpose register rB are moved into the special register "
|
"identified by the sum of general-purpose register rA and the immediate value.",
|
"defined by contents of general-purpose register rA logically ORed with the immediate value.",
|
"spr(rA OR Immediate) <- rB[31:0]",
|
"spr(rA OR Immediate) <- rB[31:0]",
|
"spr(rA OR Immediate) <- rB[31:0]",
|
"spr(rA OR Immediate) <- rB[31:0]",
|
"None", ORBIS32I,},
|
"None", ORBIS32I,},
|
|
|
{"l.mfspr", "Move From Special-Purpose Register",
|
{"l.mfspr", "Move From Special-Purpose Register",
|
"The contents of the special register are identified by the sum of general-purpose rA, and "
|
"The contents of the special register, defined by contents of general-purpose rA logically ORed "
|
"the immediate value are moved into general-purpose register rD.",
|
"with immediate value, are moved into general-purpose register rD.",
|
"rD[31:0] <- spr(rA OR Immediate)",
|
"rD[31:0] <- spr(rA OR Immediate)",
|
"rD[63:0] <- spr(rA OR Immediate)",
|
"rD[63:0] <- spr(rA OR Immediate)",
|
"None", ORBIS32I,},
|
"None", ORBIS32I,},
|
|
|
{"l.nop", "No Operation",
|
{"l.nop", "No Operation",
|
| Line 695... |
Line 718... |
{"l.j", "Jump",
|
{"l.j", "Jump",
|
"The immediate value is shifted left two bits, sign-extended to "
|
"The immediate value is shifted left two bits, sign-extended to "
|
"program counter width, and then added to the address of the jump instruction. The result "
|
"program counter width, and then added to the address of the jump instruction. The result "
|
"is the effective address of the jump. The program unconditionally jumps "
|
"is the effective address of the jump. The program unconditionally jumps "
|
"to EA with a delay of one instruction.",
|
"to EA with a delay of one instruction.",
|
"PC <- exts(Immediate << 2) + JumpInsnAddr\\LR <- DelayInsnAddr + 4",
|
"PC <- exts(Immediate << 2) + JumpInsnAddr",
|
"PC <- exts(Immediate << 2) + JumpInsnAddr\\LR <- DelayInsnAddr + 4",
|
"PC <- exts(Immediate << 2) + JumpInsnAddr",
|
"None", ORBIS32I,},
|
"None", ORBIS32I,},
|
|
|
{"l.jalr", "Jump and Link Register",
|
{"l.jalr", "Jump and Link Register",
|
"The contents of general-purpose register rB "
|
"The contents of general-purpose register rB "
|
"is the effective address of the jump. The program unconditionally jumps "
|
"is the effective address of the jump. The program unconditionally jumps "
|
"to EA with a delay of one instruction. The "
|
"to EA with a delay of one instruction. The "
|
"address of the instruction after the delay slot is placed in the "
|
"address of the instruction after the delay slot is placed in the "
|
"link register.",
|
"link register. It is not allowed to specify link register as rB.",
|
"PC <- rB\\LR <- DelayInsnAddr + 4",
|
"PC <- rB\\LR <- DelayInsnAddr + 4",
|
"PC <- rB\\LR <- DelayInsnAddr + 4",
|
"PC <- rB\\LR <- DelayInsnAddr + 4",
|
"None", ORBIS32I,},
|
"None", ORBIS32I,},
|
|
|
{"l.jr", "Jump Register",
|
{"l.jr", "Jump Register",
|
| Line 830... |
Line 853... |
{"lf.add.s", "Add Floating-Point Single-Precision",
|
{"lf.add.s", "Add Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA are added to the contents "
|
"The contents of vector/floating-point register vfrA are added to the contents "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"vfrD[31:0] <- vfrA[31:0] + vfrB[31:0]",
|
"vfrD[31:0] <- vfrA[31:0] + vfrB[31:0]",
|
"N/A",
|
"vfrD[31:0] <- vfrA[31:0] + vfrB[31:0]\\vfrD[63:32] <- 0",
|
"None", ORFPX32I,},
|
"Floating Point", ORFPX32I,},
|
|
|
{"lf.sub.s", "Subtract Floating-Point Single-Precision",
|
{"lf.sub.s", "Subtract Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrB are subtracted from the contents "
|
"The contents of vector/floating-point register vfrB are subtracted from the contents "
|
"of vector/floating-point register vfrA to form the result. The result is placed into "
|
"of vector/floating-point register vfrA to form the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"vfrD[31:0] <- vfrA[31:0] - vfrB[31:0]",
|
"vfrD[31:0] <- vfrA[31:0] - vfrB[31:0]",
|
"N/A",
|
"vfrD[31:0] <- vfrA[31:0] - vfrB[31:0]\\vfrD[63:32] <- 0",
|
"None", ORFPX32I,},
|
"Floating Point", ORFPX32I,},
|
|
|
{"lf.mul.s", "Multiply Floating-Point Single-Precision",
|
{"lf.mul.s", "Multiply Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA are multiplied by the contents "
|
"The contents of vector/floating-point register vfrA are multiplied by the contents "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"vfrD[31:0] <- vfrA[31:0] * vfrB[31:0]",
|
"vfrD[31:0] <- vfrA[31:0] * vfrB[31:0]",
|
"N/A",
|
"vfrD[31:0] <- vfrA[31:0] * vfrB[31:0]\\vfrD[63:32] <- 0",
|
"None", ORFPX32I,},
|
"Floating Point", ORFPX32I,},
|
|
|
{"lf.div.s", "Divide Floating-Point Single-Precision",
|
{"lf.div.s", "Divide Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA are divided by the contents "
|
"The contents of vector/floating-point register vfrA are divided by the contents "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"vfrD[31:0] <- vfrA[31:0] / vfrB[31:0]",
|
"vfrD[31:0] <- vfrA[31:0] / vfrB[31:0]",
|
"N/A",
|
"vfrD[31:0] <- vfrA[31:0] / vfrB[31:0]\\vfrD[63:32] <- 0",
|
"None", ORFPX32II,},
|
"Floating Point", ORFPX32II,},
|
|
|
{"lf.rem.s", "Remainder Floating-Point Single-Precision",
|
{"lf.rem.s", "Remainder Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA are divided by the contents "
|
"The contents of vector/floating-point register vfrA are divided by the contents "
|
"of vector/floating-point register vfrB, and remainder is used as the result. The result is placed into "
|
"of vector/floating-point register vfrB, and remainder is used as the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"vfrD[31:0] <- vfrA[31:0] % vfrB[31:0]",
|
"vfrD[31:0] <- vfrA[31:0] % vfrB[31:0]",
|
"N/A",
|
"vfrD[31:0] <- vfrA[31:0] % vfrB[31:0]\\vfrD[63:32] <- 0",
|
"None", ORFPX32II,},
|
"Floating Point", ORFPX32II,},
|
|
|
{"lf.madd.s", "Multiply and Add Floating-Point Single-Precision",
|
{"lf.madd.s", "Multiply and Add Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA are multiplied by the contents "
|
"The contents of vector/floating-point register vfrA are multiplied by the contents "
|
"of vector/floating-point register vfrB, and added to special-purpose register "
|
"of vector/floating-point register vfrB, and added to special-purpose register "
|
"FPMADDLO/FPMADDHI.",
|
"FPMADDLO/FPMADDHI.",
|
"FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[31:0] * vfrB[31:0] + FPMADDHI[31:0]FPMADDLO[31:0]",
|
"FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[31:0] * vfrB[31:0] + FPMADDHI[31:0]FPMADDLO[31:0]",
|
"N/A",
|
"FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[31:0] * vfrB[31:0] + FPMADDHI[31:0]FPMADDLO[31:0]\\FPMADDHI <- 0\\FPMADDLO <- 0",
|
"None", ORFPX32II,},
|
"Floating Point", ORFPX32II,},
|
|
|
{"lf.sfeq.s", "Set Flag if Equal Floating-Point Single-Precision",
|
{"lf.sfeq.s", "Set Flag if Equal Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"vector/floating-point register vfrB are compared. If the two registers are equal, "
|
"vector/floating-point register vfrB are compared. If the two registers are equal, "
|
"the compare flag is set; otherwise the compare flag is cleared.",
|
"the compare flag is set; otherwise the compare flag is cleared.",
|
"SR[F] <- vfrA[31:0] == vfrB[31:0]",
|
"SR[F] <- vfrA[31:0] == vfrB[31:0]",
|
"N/A",
|
"SR[F] <- vfrA[31:0] == vfrB[31:0]",
|
"None", ORFPX32I,},
|
"None", ORFPX32I,},
|
|
|
{"lf.sfne.s", "Set Flag if Not Equal Floating-Point Single-Precision",
|
{"lf.sfne.s", "Set Flag if Not Equal Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"vector/floating-point register vfrB are compared. If the two registers are not equal, "
|
"vector/floating-point register vfrB are compared. If the two registers are not equal, "
|
"the compare flag is set; otherwise the compare flag is cleared.",
|
"the compare flag is set; otherwise the compare flag is cleared.",
|
"SR[F] <- vfrA[31:0] != vfrB[31:0]",
|
"SR[F] <- vfrA[31:0] != vfrB[31:0]",
|
"N/A",
|
"SR[F] <- vfrA[31:0] != vfrB[31:0]",
|
"None", ORFPX32I,},
|
"None", ORFPX32I,},
|
|
|
{"lf.sfgt.s", "Set Flag if Greater Than Floating-Point Single-Precision",
|
{"lf.sfgt.s", "Set Flag if Greater Than Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"vector/floating-point register vfrB are compared. If the first register is greater than "
|
"vector/floating-point register vfrB are compared. If the first register is greater than "
|
"the second register, the compare flag is set; otherwise the compare flag is cleared.",
|
"the second register, the compare flag is set; otherwise the compare flag is cleared.",
|
"SR[F] <- vfrA[31:0] > vfrB[31:0]",
|
"SR[F] <- vfrA[31:0] > vfrB[31:0]",
|
"N/A",
|
"SR[F] <- vfrA[31:0] > vfrB[31:0]",
|
"None", ORFPX32I,},
|
"None", ORFPX32I,},
|
|
|
{"lf.sfge.s", "Set Flag if Greater or Equal Than Floating-Point Single-Precision",
|
{"lf.sfge.s", "Set Flag if Greater or Equal Than Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"vector/floating-point register vfrB are compared. If the first register is greater than "
|
"vector/floating-point register vfrB are compared. If the first register is greater than "
|
"or equal to the second register, the compare flag is set; otherwise the compare flag is cleared.",
|
"or equal to the second register, the compare flag is set; otherwise the compare flag is cleared.",
|
"SR[F] <- vfrA[31:0] >= vfrB[31:0]",
|
"SR[F] <- vfrA[31:0] >= vfrB[31:0]",
|
"N/A",
|
"SR[F] <- vfrA[31:0] >= vfrB[31:0]",
|
"None", ORFPX32I,},
|
"None", ORFPX32I,},
|
|
|
{"lf.sflt.s", "Set Flag if Less Than Floating-Point Single-Precision",
|
{"lf.sflt.s", "Set Flag if Less Than Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"vector/floating-point register vfrB are compared. If the first register is less than the "
|
"vector/floating-point register vfrB are compared. If the first register is less than the "
|
"second register, the compare flag is set; otherwise the compare flag is cleared.",
|
"second register, the compare flag is set; otherwise the compare flag is cleared.",
|
"SR[F] <- vfrA[31:0] < vfrB[31:0]",
|
"SR[F] <- vfrA[31:0] < vfrB[31:0]",
|
"N/A",
|
"SR[F] <- vfrA[31:0] < vfrB[31:0]",
|
"None", ORFPX32I,},
|
"None", ORFPX32I,},
|
|
|
{"lf.sfle.s", "Set Flag if Less or Equal Than Floating-Point Single-Precision",
|
{"lf.sfle.s", "Set Flag if Less or Equal Than Floating-Point Single-Precision",
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"vector/floating-point register vfrB are compared. If the first register is less than "
|
"vector/floating-point register vfrB are compared. If the first register is less than "
|
"or equal to the second register, the compare flag is set; otherwise the compare flag is cleared.",
|
"or equal to the second register, the compare flag is set; otherwise the compare flag is cleared.",
|
"SR[F] <- vfrA[31:0] <= vfrB[31:0]",
|
"SR[F] <- vfrA[31:0] <= vfrB[31:0]",
|
"N/A",
|
"SR[F] <- vfrA[31:0] <= vfrB[31:0]",
|
"None", ORFPX32I,},
|
"None", ORFPX32I,},
|
|
|
{"lf.ftoi.s", "Floating-Point Single-Precision To Integer",
|
{"lf.ftoi.s", "Floating-Point Single-Precision To Integer",
|
"The contents of vector/floating-point register vfrA are converted to an integer "
|
"The contents of vector/floating-point register vfrA are converted to an integer "
|
"and stored into general-purpose register rD.",
|
"and stored into general-purpose register rD.",
|
"rD[31:0] <- ftoi(vfrA[31:0])",
|
"rD[31:0] <- ftoi(vfrA[31:0])",
|
"N/A",
|
"rD[31:0] <- ftoi(vfrA[31:0])\\rD[63:32] <- 0",
|
"None", ORFPX32I,},
|
"Floating Point", ORFPX32I,},
|
|
|
{"lf.itof.s", "Integer To Floating-Point Single-Precision",
|
{"lf.itof.s", "Integer To Floating-Point Single-Precision",
|
"The contents of general-purpose register rA are converted to a single-precision "
|
"The contents of general-purpose register rA are converted to a single-precision "
|
"floating-point number and stored into vector/floating-point register vfrD.",
|
"floating-point number and stored into vector/floating-point register vfrD.",
|
"vfrD[31:0] <- itof(rA[31:0])",
|
"vfrD[31:0] <- itof(rA[31:0])",
|
"N/A",
|
"vfrD[31:0] <- itof(rA[31:0])\\vfrD[63:32] <- 0",
|
"None", ORFPX32I,},
|
"Floating Point", ORFPX32I,},
|
|
|
{"lf.cust1.s", "Reserved for ORFPX32 Custom Instructions",
|
{"lf.cust1.s", "Reserved for ORFPX32 Custom Instructions",
|
"This fake instruction only allocates instruction set space for custom instructions. "
|
"This fake instruction only allocates instruction set space for custom instructions. "
|
"Custom instructions are those that are not defined by the architecture but instead "
|
"Custom instructions are those that are not defined by the architecture but instead "
|
"by the implementation itself.",
|
"by the implementation itself.",
|
| Line 951... |
Line 974... |
"The contents of vector/floating-point register vfrA are added to the contents "
|
"The contents of vector/floating-point register vfrA are added to the contents "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"N/A",
|
"N/A",
|
"vfrD[63:0] <- vfrA[63:0] + vfrB[63:0]",
|
"vfrD[63:0] <- vfrA[63:0] + vfrB[63:0]",
|
"None", ORFPX64I,},
|
"Floating Point", ORFPX64I,},
|
|
|
{"lf.sub.d", "Subtract Floating-Point Double-Precision",
|
{"lf.sub.d", "Subtract Floating-Point Double-Precision",
|
"The contents of vector/floating-point register vfrB are subtracted from the contents "
|
"The contents of vector/floating-point register vfrB are subtracted from the contents "
|
"of vector/floating-point register vfrA to form the result. The result is placed into "
|
"of vector/floating-point register vfrA to form the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"N/A",
|
"N/A",
|
"vfrD[63:0] <- vfrA[63:0] - vfrB[63:0]",
|
"vfrD[63:0] <- vfrA[63:0] - vfrB[63:0]",
|
"None", ORFPX64I,},
|
"Floating Point", ORFPX64I,},
|
|
|
{"lf.mul.d", "Multiply Floating-Point Double-Precision",
|
{"lf.mul.d", "Multiply Floating-Point Double-Precision",
|
"The contents of vector/floating-point register vfrA are multiplied by the contents "
|
"The contents of vector/floating-point register vfrA are multiplied by the contents "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"N/A",
|
"N/A",
|
"vfrD[63:0] <- vfrA[63:0] * vfrB[63:0]",
|
"vfrD[63:0] <- vfrA[63:0] * vfrB[63:0]",
|
"None", ORFPX64I,},
|
"Floating Point", ORFPX64I,},
|
|
|
{"lf.div.d", "Divide Floating-Point Double-Precision",
|
{"lf.div.d", "Divide Floating-Point Double-Precision",
|
"The contents of vector/floating-point register vfrA are divided by the contents "
|
"The contents of vector/floating-point register vfrA are divided by the contents "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"of vector/floating-point register vfrB to form the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"N/A",
|
"N/A",
|
"vfrD[63:0] <- vfrA[63:0] / vfrB[63:0]",
|
"vfrD[63:0] <- vfrA[63:0] / vfrB[63:0]",
|
"None", ORFPX64II,},
|
"Floating Point", ORFPX64II,},
|
|
|
{"lf.rem.d", "Remainder Floating-Point Double-Precision",
|
{"lf.rem.d", "Remainder Floating-Point Double-Precision",
|
"The contents of vector/floating-point register vfrA are divided by the contents "
|
"The contents of vector/floating-point register vfrA are divided by the contents "
|
"of vector/floating-point register vfrB, and remainder is used as the result. The result is placed into "
|
"of vector/floating-point register vfrB, and remainder is used as the result. The result is placed into "
|
"vector/floating-point register vfrD.",
|
"vector/floating-point register vfrD.",
|
"N/A",
|
"N/A",
|
"vfrD[63:0] <- vfrA[63:0] % vfrB[63:0]",
|
"vfrD[63:0] <- vfrA[63:0] % vfrB[63:0]",
|
"None", ORFPX64II,},
|
"Floating Point", ORFPX64II,},
|
|
|
{"lf.madd.d", "Multiply and Add Floating-Point Double-Precision",
|
{"lf.madd.d", "Multiply and Add Floating-Point Double-Precision",
|
"The contents of vector/floating-point register vfrA are multiplied by the contents "
|
"The contents of vector/floating-point register vfrA are multiplied by the contents "
|
"of vector/floating-point register vfrB, and added to special-purpose register "
|
"of vector/floating-point register vfrB, and added to special-purpose register "
|
"FPMADDLO/FPMADDHI.",
|
"FPMADDLO/FPMADDHI.",
|
"N/A",
|
"N/A",
|
"FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[63:0] * vfrB[63:0] + FPMADDHI[31:0]FPMADDLO[31:0]",
|
"FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[63:0] * vfrB[63:0] + FPMADDHI[31:0]FPMADDLO[31:0]",
|
"None", ORFPX64II,},
|
"Floating Point", ORFPX64II,},
|
|
|
{"lf.sfeq.d", "Set Flag if Equal Floating-Point Double-Precision",
|
{"lf.sfeq.d", "Set Flag if Equal Floating-Point Double-Precision",
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"The contents of vector/floating-point register vfrA and the contents of "
|
"vector/floating-point register vfrB are compared. If the two registers are equal, "
|
"vector/floating-point register vfrB are compared. If the two registers are equal, "
|
"the compare flag is set; otherwise the compare flag is cleared.",
|
"the compare flag is set; otherwise the compare flag is cleared.",
|
| Line 1046... |
Line 1069... |
{"lf.ftoi.d", "Floating-Point Double-Precision To Integer",
|
{"lf.ftoi.d", "Floating-Point Double-Precision To Integer",
|
"The contents of vector/floating-point register vfrA are converted to an integer "
|
"The contents of vector/floating-point register vfrA are converted to an integer "
|
"and stored in general-purpose register rD.",
|
"and stored in general-purpose register rD.",
|
"N/A",
|
"N/A",
|
"rD[63:0] <- ftoi(vfrA[63:0])",
|
"rD[63:0] <- ftoi(vfrA[63:0])",
|
"None", ORFPX64I,},
|
"Floating Point", ORFPX64I,},
|
|
|
{"lf.itof.d", "Integer To Floating-Point Double-Precision",
|
{"lf.itof.d", "Integer To Floating-Point Double-Precision",
|
"The contents of general-purpose register rA are converted to a double-precision "
|
"The contents of general-purpose register rA are converted to a double-precision "
|
"floating-point number and stored in vector/floating-point register vfrD.",
|
"floating-point number and stored in vector/floating-point register vfrD.",
|
"N/A",
|
"N/A",
|
"vfrD[63:0] <- itof(rA[63:0])",
|
"vfrD[63:0] <- itof(rA[63:0])",
|
"None", ORFPX64I,},
|
"Floating Point", ORFPX64I,},
|
|
|
{"lf.cust1.d", "Reserved for ORFPX64 Custom Instructions",
|
{"lf.cust1.d", "Reserved for ORFPX64 Custom Instructions",
|
"This fake instruction only allocates instruction set space for custom instructions. "
|
"This fake instruction only allocates instruction set space for custom instructions. "
|
"Custom instructions are those that are not defined by the architecture but instead "
|
"Custom instructions are those that are not defined by the architecture but instead "
|
"by the implementation itself.",
|
"by the implementation itself.",
|
| Line 2397... |
Line 2420... |
"The contents of vector/floating-point "
|
"The contents of vector/floating-point "
|
"register vfrA are used as an effective address. The double word in memory "
|
"register vfrA are used as an effective address. The double word in memory "
|
"addressed by EA is loaded into vector/floating-point register vfrD. ",
|
"addressed by EA is loaded into vector/floating-point register vfrD. ",
|
"N/A",
|
"N/A",
|
"EA <- vfrA[63:0]\\vfrD[63:0] <- (EA)[63:0]",
|
"EA <- vfrA[63:0]\\vfrD[63:0] <- (EA)[63:0]",
|
"TLB miss\\Page fault\\Bus error", ORFPX64I,},
|
"TLB miss\\Page fault\\Bus error\\Alignment", ORFPX64I,},
|
|
|
{"lvf.lw", "Load Vector/Floating-Point Single Word",
|
{"lvf.lw", "Load Vector/Floating-Point Single Word",
|
"The contents of vector/floating-point "
|
"The contents of vector/floating-point "
|
"register vfrA are used as an effective address. The double word in memory "
|
"register vfrA are used as an effective address. The double word in memory "
|
"addressed by EA is loaded into vector/floating-point register vfrD. ",
|
"addressed by EA is loaded into vector/floating-point register vfrD. ",
|
"EA <- vfrA[31:0]\\vfrD[31:0] <- (EA)[31:0]",
|
"EA <- vfrA[31:0]\\vfrD[31:0] <- (EA)[31:0]",
|
"EA <- vfrA[31:0]\\vfrD[31:0] <- (EA)[31:0]",
|
"EA <- vfrA[31:0]\\vfrD[31:0] <- (EA)[31:0]",
|
"TLB miss\\Page fault\\Bus error", ORFPX32I,},
|
"TLB miss\\Page fault\\Bus error\\Alignment", ORFPX32I,},
|
|
|
{"lvf.sd", "Store Vector/Floating-Point Double Word",
|
{"lvf.sd", "Store Vector/Floating-Point Double Word",
|
"The contents of vector/floating-point "
|
"The contents of vector/floating-point "
|
"register vfrA are used as an effective address. The double word in vector/floating-point "
|
"register vfrA are used as an effective address. The double word in vector/floating-point "
|
"register vrfB is stored to the memory location addressed by EA. ",
|
"register vrfB is stored to the memory location addressed by EA. ",
|
"N/A",
|
"N/A",
|
"EA <- vfrA[63:0]\\vfrD[63:0] <- (EA)[63:0]",
|
"EA <- vfrA[63:0]\\vfrD[63:0] <- (EA)[63:0]",
|
"TLB miss\\Page fault\\Bus error", ORFPX64I,},
|
"TLB miss\\Page fault\\Bus error\\Alignment", ORFPX64I,},
|
|
|
{"lvf.sw", "Store Vector/Floating-Point Single Word",
|
{"lvf.sw", "Store Vector/Floating-Point Single Word",
|
"The contents of vector/floating-point "
|
"The contents of vector/floating-point "
|
"register vfrA are used as an effective address. The single word in vector/floating-point "
|
"register vfrA are used as an effective address. The single word in vector/floating-point "
|
"register vrfB is stored to the memory location addressed by EA. ",
|
"register vrfB is stored to the memory location addressed by EA. ",
|
"EA <- vfrA[31:0]\\vfrD[31:0] <- (EA)[31:0]",
|
"EA <- vfrA[31:0]\\vfrD[31:0] <- (EA)[31:0]",
|
"EA <- vfrA[31:0]\\vfrD[31:0] <- (EA)[31:0]",
|
"EA <- vfrA[31:0]\\vfrD[31:0] <- (EA)[31:0]",
|
"TLB miss\\Page fault\\Bus error", ORFPX32I,},
|
"TLB miss\\Page fault\\Bus error\\Alignment", ORFPX32I,},
|
|
|
{"", "", "", "", "", "", 0}
|
{"", "", "", "", "", "", 0}
|
|
|
};
|
};
|
|
|
