| Line 35... |
Line 35... |
unsigned int UPR;
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unsigned int UPR;
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/* Number of total available matchpoints in this implementation. */
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/* Number of total available matchpoints in this implementation. */
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unsigned int num_matchpoints;
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unsigned int num_matchpoints;
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/* Number of currently used matchpoints. */
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/* Number of currently used matchpoints. */
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unsigned int num_used_matchpoints;
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unsigned int num_used_matchpoints;
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/* Has watchpoint driven counters. */
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int has_counters;
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/* Number of registers. */
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/* Number of registers. */
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unsigned int num_gpr_regs;
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unsigned int num_gpr_regs;
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unsigned int num_vf_regs;
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unsigned int num_vfpr_regs;
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/* Is there any vf support? */
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int vf_present;
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int vf_present;
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};
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};
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struct or1k_target_ops
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struct or1k_target_ops
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{
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{
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| Line 89... |
Line 92... |
/* Special purpose regisers. */
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/* Special purpose regisers. */
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#define SPR_GROUP_SIZE_BITS (11)
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#define SPR_GROUP_SIZE_BITS (11)
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#define SPR_GROUP_SIZE (1 << SPR_GROUP_SIZE_BITS)
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#define SPR_GROUP_SIZE (1 << SPR_GROUP_SIZE_BITS)
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#define SPR_SYSTEM_GROUP (0)
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#define SPR_SYSTEM_GROUP (0)
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#define SPR_DEBUG_GROUP (6)
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#define SPR_DEBUG_GROUP (6)
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#define SPR_GPR (1024)
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#define SPR_GPR_START (1024)
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#define SPR_VFPR ((MAX_CID + 1) * MAX_GPR_REGS + SPR_GPR)
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#define SPR_VFPR_START ((MAX_CID + 1) * MAX_GPR_REGS + SPR_GPR_START)
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#define OR1K_NUM_SPR_GROUPS (11)
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#define OR1K_NUM_SPR_GROUPS (12)
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/* Define register values. */
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/* Define register values. */
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#define SPR_REG(group, index) (((group) << SPR_GROUP_SIZE_BITS) + (index))
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#define SPR_REG(group, index) (((group) << SPR_GROUP_SIZE_BITS) + (index))
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#define VR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 1)
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#define VR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 0)
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#define UPR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
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#define UPR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 1)
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#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 3)
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#define CPUCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
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#define DCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 7)
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#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 16)
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#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 17)
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#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid))
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#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid))
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#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 0)
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#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 32)
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#define DCR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 8)
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#define DCR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 40)
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#define DMR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 16)
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#define DMR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 48)
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#define DMR2_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 17)
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#define DMR2_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 49)
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#define DCWR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 18)
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#define DCWR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 50)
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#define DCWR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 19)
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#define DCWR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 51)
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#define DSR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 20)
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#define DSR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 52)
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#define DRR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 21)
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#define DRR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 53)
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#define DIR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 22)
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#define DIR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 54)
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#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
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#define ZERO_REGNUM (0)
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#define ZERO_REGNUM (0)
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#define SP_REGNUM (1)
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#define SP_REGNUM (1)
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#define FP_REGNUM (2)
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#define FP_REGNUM (2)
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#define A0_REGNUM (3)
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#define A0_REGNUM (3)
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#define A5_REGNUM (8)
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#define A5_REGNUM (8)
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