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#endif
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#endif
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#include "defs.h"
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#include "defs.h"
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#include <inttypes.h> /* CZ */
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#include <inttypes.h> /* CZ */
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/* CZ 11/09/01 -- Cause GDB to expect actual PC value to appear
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in breakpoint exception vector instead of being in PC itself */
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#define NEW_PC_HANDLING
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#ifdef NEW_PC_HANDLING
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#define TARGET_READ_PC(pid) or1k_target_read_pc(pid)
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#define TARGET_WRITE_PC(pc,pid) or1k_target_write_pc(pc,pid)
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#endif
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struct value;
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struct value;
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struct struct_or1k_implementation
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struct struct_or1k_implementation
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{
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{
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/* Implementation version. */
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/* Implementation version. */
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#define PC_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 0)
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#define PC_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 0)
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#define PS_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 1)
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#define PS_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 1)
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#define EPCR_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 2)
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#define EPCR_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 2)
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#define CCR_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 2)
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#define CCR_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 2)
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/*******************************************/
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/* Added by CZ on 12/09/01 Used for new style breakpoints */
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/* These really aren't designed to be seen by the user */
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#define EPC_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 3)
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#define EAR_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 4)
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#define ESR_REGNUM (MAX_GPR_REGS + MAX_VF_REGS + 5)
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#define EPC_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP,32+cid)
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#define EAR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP,48+cid)
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#define ESR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP,64+cid)
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#define MAX_EXTRA_NUM_REGS 6
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/******** END OF ADDITIONS BY CZ ************/
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/******** END OF ADDITIONS BY CZ ************/
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extern int or1k_regnum_to_sprnum PARAMS ((int regno));
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extern int or1k_regnum_to_sprnum PARAMS ((int regno));
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#define REGNUM_TO_SPRNUM(regno) (or1k_regnum_to_sprnum(regno))
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#define REGNUM_TO_SPRNUM(regno) (or1k_regnum_to_sprnum(regno))
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/* Defines for SPR bits. */
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/* Defines for SPR bits. */
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#define DMR1_ST (0x00400000)
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#define DMR1_ST (0x00400000)
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/* Changed by CZ 21/06/01 */
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/* Changed by CZ 21/06/01 */
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#define DRR_BE2 (0x00002000)
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#define DRR_TE (0x00002000)
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#define DRR_BE (0x00001000)
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#define DRR_BE (0x00001000)
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#define DRR_SCE (0x00000800)
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#define DRR_SCE (0x00000800)
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#define DRR_RE (0x00000400)
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#define DRR_RE (0x00000400)
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#define DRR_IME (0x00000200)
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#define DRR_IME (0x00000200)
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#define DRR_DME (0x00000100)
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#define DRR_DME (0x00000100)
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/* Number of machine VF registers */
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/* Number of machine VF registers */
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#define NUM_VF_REGS (or1k_implementation.num_vfpr_regs)
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#define NUM_VF_REGS (or1k_implementation.num_vfpr_regs)
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#define MAX_VF_REGS (32)
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#define MAX_VF_REGS (32)
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/*******************************/
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/* Paramterized by CZ 11/09/01 */
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/*******************************/
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/* gdb mapping of registers */
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/* gdb mapping of registers */
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#ifndef NUM_REGS
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#ifndef NUM_REGS
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#define NUM_REGS (MAX_GPR_REGS+MAX_VF_REGS+MAX_EXTRA_NUM_REGS)
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#define NUM_REGS (MAX_GPR_REGS+MAX_VF_REGS+3)
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#endif
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#endif
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/* Can act like a little or big endian. */
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/* Can act like a little or big endian. */
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#if !defined (TARGET_BYTE_ORDER_DEFAULT)
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#if !defined (TARGET_BYTE_ORDER_DEFAULT)
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#define TARGET_BYTE_ORDER_DEFAULT BIG_ENDIAN
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#define TARGET_BYTE_ORDER_DEFAULT BIG_ENDIAN
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/* Amount PC must be decremented by after a breakpoint.
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/* Amount PC must be decremented by after a breakpoint.
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This is often the number of bytes in BREAKPOINT
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This is often the number of bytes in BREAKPOINT
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but not always. */
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but not always. */
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/* Note: several attempts have been made to account for
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differences between hardware and software breakpoints
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and still allow hardware breakpoints to advance the
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PC beyond the offending instruction. However, short
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of rewriting gdb, none of them seem to work. Thus,
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for now, we assume that a hardware breakpoint will
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always give control to the breakpoint vector BEFORE
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it executes the instruction, thus, when the breakpoint
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vector returns, it will return to the same instruction
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that caused the exception (and thus hit the exception
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again if it hasn't been cleared) Note that if it actually
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executes this instruction, things fail bandly inside of
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gdb. This should not be an issue for now, as the or1200
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implementation will not implement hardware breakpoints
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at all.. */
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#define DECR_PC_AFTER_BREAK 0
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#define DECR_PC_AFTER_BREAK 0
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extern int or1k_insert_breakpoint (CORE_ADDR addr, char *contents_cache);
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extern int or1k_insert_breakpoint (CORE_ADDR addr, char *contents_cache);
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#define target_insert_hw_breakpoint(addr, cache) or1k_insert_breakpoint (addr, cache)
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#define target_insert_hw_breakpoint(addr, cache) or1k_insert_breakpoint (addr, cache)
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