| Line 38... |
Line 38... |
|
|
/* *INDENT-OFF* */
|
/* *INDENT-OFF* */
|
|
|
/* Group reg name size. See or1k_reg_names. */
|
/* Group reg name size. See or1k_reg_names. */
|
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = {
|
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = {
|
64, 0, 0, 6, 6, 2, (24+32+32), 16, 1, 3, 2};
|
80, 0, 0, 6, 4, 2,
|
|
23, 16, 1, 3, 2, 8};
|
|
|
/* Generated reg names. See or1k_spr_reg_name. */
|
int or1k_group_name_start[OR1K_NUM_SPR_GROUPS] = {
|
|
0, 0, 0, 253, 254, 256,
|
|
32, 248, 16, 16, 255, 0};
|
|
|
|
/* Generated reg names (max valid alias index).
|
|
See or1k_spr_reg_name. */
|
int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = {
|
int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = {
|
64, 515, 515, 6, 6, 2, (24+32+32), 16, 1, 3, 2};
|
2047+1, 2047+1, 2047+1, 258+1, 257+1, 257+1,
|
|
79+1, 263+1, 16+1, 18+1, 256+1, 7+1};
|
|
|
/* Register names. */
|
/* Register names. */
|
char *or1k_reg_names[] = {
|
char *or1k_reg_names[] = {
|
/* group 0 - general*/
|
/* group 0 - general*/
|
"UPR", "VR", "PC", "SR", "EPCR0", "SPR0_5", "SPR0_6", "SPR0_7",
|
"VR", "UPR", "CPUCFGR", "DMMUCFGR", "IMMUCFGR", "DCCFGR", "ICCFGR", "DCFGR",
|
"SPR0_8", "SPR0_9", "SPR0_10", "SPR0_11", "SPR0_12", "SPR0_13", "SPR0_14", "SPR0_15",
|
"PCCFGR", "SPR0_9", "SPR0_10", "SPR0_11", "SPR0_12", "SPR0_13", "SPR0_14", "SPR0_15",
|
|
"PC", "SR", "SPR0_18", "SPR0_19", "SPR0_20", "SPR0_21", "SPR0_22", "SPR0_23",
|
"EPCR0", "EPCR1", "EPCR2", "EPCR3", "EPCR4", "EPCR5", "EPCR6", "EPCR7",
|
"EPCR0", "EPCR1", "EPCR2", "EPCR3", "EPCR4", "EPCR5", "EPCR6", "EPCR7",
|
"EPCR8", "EPCR9", "EPCR10", "EPCR11", "EPCR12", "EPCR13", "EPCR14", "EPCR15",
|
"EPCR8", "EPCR9", "EPCR10", "EPCR11", "EPCR12", "EPCR13", "EPCR14", "EPCR15",
|
"EEAR0","EEAR1", "EEAR2", "EEAR3", "EEAR4", "EEAR5", "EEAR6", "EEAR7",
|
"EEAR0","EEAR1", "EEAR2", "EEAR3", "EEAR4", "EEAR5", "EEAR6", "EEAR7",
|
"EEAR8", "EEAR9", "EEAR10", "EEAR11", "EEAR12", "EEAR13", "EEAR14", "EEAR15",
|
"EEAR8", "EEAR9", "EEAR10", "EEAR11", "EEAR12", "EEAR13", "EEAR14", "EEAR15",
|
"ESR0", "ESR1", "ESR2", "ESR3", "ESR4", "ESR5", "ESR6", "ESR7",
|
"ESR0", "ESR1", "ESR2", "ESR3", "ESR4", "ESR5", "ESR6", "ESR7",
|
"ESR8", "ESR9", "ESR10", "ESR11", "ESR12", "ESR13", "ESR14", "ESR15",
|
"ESR8", "ESR9", "ESR10", "ESR11", "ESR12", "ESR13", "ESR14", "ESR15",
|
/* gpr+vf registers generated */
|
/* gpr+vf registers generated */
|
/* group 1 - Data MMU - not listed, generated */
|
/* group 1 - Data MMU - not listed, generated */
|
/* group 2 - Instruction MMU - not listed, generated */
|
/* group 2 - Instruction MMU - not listed, generated */
|
/* group 3 - Data cache */
|
/* group 3 - Data cache */
|
"DCCR", "DCBPR", "DCBFR", "DCBIR", "DCBWR", "DCBLR",
|
"DCCR", "DCBIR", "DCBPR", "DCBFR", "DCBWR", "DCBLR",
|
/* group 4 - Instruction cache */
|
/* group 4 - Instruction cache */
|
"ICCR", "ICBPR", "ICBFR", "ICBIR", "ICBWR", "ICBLR",
|
"ICCR", "ICBLR", "ICBIR", "ICBPR",
|
/* group 5 - MAC */
|
/* group 5 - MAC */
|
"MACLO", "MACHI",
|
"MACLO", "MACHI",
|
/* group 6 - debug */
|
/* group 6 - debug */
|
"DVR0", "DVR1", "DVR2", "DVR3", "DVR4", "DVR5", "DVR6", "DVR7",
|
"DVR0", "DVR1", "DVR2", "DVR3", "DVR4", "DVR5", "DVR6", "DVR7",
|
"DCR0", "DCR1", "DCR2", "DCR3", "DCR4", "DCR5", "DCR6", "DCR7",
|
"DCR0", "DCR1", "DCR2", "DCR3", "DCR4", "DCR5", "DCR6", "DCR7",
|
"DMR1", "DMR2", "DCWR0","DCWR1", "DSR", "DRR", "PC", "SPR6_23",
|
"DMR1", "DMR2", "DCWR0","DCWR1","DSR", "DRR", "DIR",
|
|
|
/* group 7 - performance counters unit */
|
/* group 7 - performance counters unit */
|
"PCCR0", "PCCR1", "PCCR2", "PCCR3", "PCCR4", "PCCR5", "PCCR6", "PCCR7",
|
|
"PCCM0", "PCMR1", "PCMR2", "PCMR3", "PCMR4", "PCMR5", "PCMR6", "PCMR7",
|
"PCCM0", "PCMR1", "PCMR2", "PCMR3", "PCMR4", "PCMR5", "PCMR6", "PCMR7",
|
|
"PCCR0", "PCCR1", "PCCR2", "PCCR3", "PCCR4", "PCCR5", "PCCR6", "PCCR7",
|
|
|
/* group 8 - power management */
|
/* group 8 - power management */
|
"PMR",
|
"PMR",
|
|
|
/* group 9 - PIC */
|
/* group 9 - PIC */
|
"PICMR", "PICPR",
|
"PICMR", "PICPR",
|
|
|
/* group 10 - tick timer */
|
/* group 10 - tick timer */
|
"TTCR", "TTIR"
|
"TTMR", "TTCR",
|
|
|
|
/* group 11 - configureation */
|
|
"CPUCFGR", "DMMUCFGR", "IMMUCFGR", "DCCFGR", "ICCFGR", "SPR11_5", "DCFGR", "PCCFGR"
|
};
|
};
|
|
|
static char *or1k_gdb_reg_names[] = {
|
static char *or1k_gdb_reg_names[] = {
|
/* general purpose registers */
|
/* general purpose registers */
|
"ZERO", "SP", "FP", "A0", "A1", "A2", "A3", "A4",
|
"ZERO", "SP", "FP", "A0", "A1", "A2", "A3", "A4",
|
| Line 137... |
Line 148... |
which are not compact, so we are mapping them for GDB. */
|
which are not compact, so we are mapping them for GDB. */
|
int
|
int
|
or1k_regnum_to_sprnum (int regno)
|
or1k_regnum_to_sprnum (int regno)
|
{
|
{
|
if (regno < MAX_GPR_REGS)
|
if (regno < MAX_GPR_REGS)
|
return SPR_REG(SPR_SYSTEM_GROUP, regno + CURRENT_CID * MAX_GPR_REGS + SPR_GPR);
|
return SPR_REG(SPR_SYSTEM_GROUP, regno + CURRENT_CID * MAX_GPR_REGS + SPR_GPR_START);
|
if (regno < MAX_GPR_REGS + MAX_VF_REGS)
|
if (regno < MAX_GPR_REGS + MAX_VF_REGS)
|
return SPR_REG(SPR_SYSTEM_GROUP, regno - MAX_GPR_REGS
|
return SPR_REG(SPR_SYSTEM_GROUP, regno - MAX_GPR_REGS
|
+ CURRENT_CID * MAX_GPR_REGS + SPR_VFPR);
|
+ CURRENT_CID * MAX_GPR_REGS + SPR_VFPR_START);
|
if (regno == PS_REGNUM)
|
if (regno == PS_REGNUM)
|
return SR_SPRNUM;
|
return SR_SPRNUM;
|
if (regno == PC_REGNUM)
|
if (regno == PC_REGNUM)
|
return PC_SPRNUM;
|
return PC_SPRNUM;
|
if (regno == CCR_REGNUM)
|
if (regno == CCR_REGNUM)
|
| Line 163... |
Line 174... |
int index = i & (SPR_GROUP_SIZE - 1);
|
int index = i & (SPR_GROUP_SIZE - 1);
|
switch (group)
|
switch (group)
|
{
|
{
|
/* Names covered in or1k_reg_names. */
|
/* Names covered in or1k_reg_names. */
|
case 0:
|
case 0:
|
|
/* Generate upper names. */
|
|
if (index >= SPR_GPR_START)
|
|
{
|
|
if (index < SPR_VFPR_START)
|
|
sprintf (tmp_name, "GPR%i", index - SPR_GPR_START);
|
|
else
|
|
sprintf (tmp_name, "VFR%i", index - SPR_VFPR_START);
|
|
return (char *)&tmp_name;
|
|
}
|
case 3:
|
case 3:
|
case 4:
|
case 4:
|
case 5:
|
case 5:
|
case 6:
|
case 6:
|
case 7:
|
case 7:
|
| Line 182... |
Line 202... |
{
|
{
|
sprintf (tmp_name, "SPR%i_%i", group, index);
|
sprintf (tmp_name, "SPR%i_%i", group, index);
|
return (char *)&tmp_name;
|
return (char *)&tmp_name;
|
}
|
}
|
else
|
else
|
return or1k_reg_names[group_start + index];
|
return or1k_reg_names[group_start + index - or1k_group_name_start[group]];
|
}
|
}
|
/* Build names for DMMU group. */
|
/* Build names for DMMU group. */
|
case 1:
|
case 1:
|
if (index < 256) {
|
case 2:
|
sprintf (tmp_name, "DTLBMR%i", index);
|
strcpy (tmp_name, (group == 1)?"D":"I");
|
return (char *)&tmp_name;
|
|
}
|
|
index -= 256;
|
|
if (index < 256) {
|
|
sprintf (tmp_name, "DTLBTR%i", index);
|
|
return (char *)&tmp_name;
|
|
}
|
|
index -= 256;
|
|
switch (index)
|
switch (index)
|
{
|
{
|
case 0:
|
case 16:
|
return "DMMUCR";
|
return strcat (tmp_name, "MMUCR");
|
case 1:
|
case 17:
|
return "DMMUPR";
|
return strcat (tmp_name, "MMUPR");
|
case 2:
|
case 18:
|
return "DTLBEIR";
|
return strcat (tmp_name, "TLBEIR");
|
|
case 24:
|
|
return strcat (tmp_name, "ATBMR0");
|
|
case 25:
|
|
return strcat (tmp_name, "ATBMR1");
|
|
case 26:
|
|
return strcat (tmp_name, "ATBMR2");
|
|
case 27:
|
|
return strcat (tmp_name, "ATBMR3");
|
|
case 28:
|
|
return strcat (tmp_name, "ATBTR0");
|
|
case 29:
|
|
return strcat (tmp_name, "ATBTR0");
|
|
case 30:
|
|
return strcat (tmp_name, "ATBTR0");
|
|
case 31:
|
|
return strcat (tmp_name, "ATBTR0");
|
default:
|
default:
|
sprintf (tmp_name, "SPR1_%i", index+512);
|
if (index >= 1024) {
|
|
index -= 1024;
|
|
sprintf (tmp_name, "%sTLBW%iMR%i", (group == 1)?"D":"I", index / 128, index % 128);
|
return (char *)&tmp_name;
|
return (char *)&tmp_name;
|
}
|
}
|
/* Build names for IMMU group. */
|
sprintf (tmp_name, "SPR%i_%i", group, index);
|
case 2:
|
|
if (index < 256) {
|
|
sprintf (tmp_name, "ITLBMR%i", index);
|
|
return (char *)&tmp_name;
|
|
}
|
|
index -= 256;
|
|
if (index < 256) {
|
|
sprintf (tmp_name, "ITLBTR%i", index);
|
|
return (char *)&tmp_name;
|
|
}
|
|
index -= 256;
|
|
switch (index)
|
|
{
|
|
case 0:
|
|
return "IMMUCR";
|
|
case 1:
|
|
return "IMMUPR";
|
|
case 2:
|
|
return "ITLBEIR";
|
|
default:
|
|
sprintf (tmp_name, "SPR1_%i", index+512);
|
|
return (char *)&tmp_name;
|
return (char *)&tmp_name;
|
}
|
}
|
default:
|
default:
|
sprintf (tmp_name, "SPR%i_%i", group, index);
|
sprintf (tmp_name, "SPR%i_%i", group, index);
|
return (char *)&tmp_name;
|
return (char *)&tmp_name;
|
| Line 884... |
Line 893... |
{
|
{
|
printf_unfiltered ("\"set or1k\" must be followed by an appropriate subcommand.\n");
|
printf_unfiltered ("\"set or1k\" must be followed by an appropriate subcommand.\n");
|
help_list (setor1kcmdlist, "set or1k ", all_commands, gdb_stdout);
|
help_list (setor1kcmdlist, "set or1k ", all_commands, gdb_stdout);
|
}
|
}
|
|
|
|
/* Parses args for spr name and puts result into group and index. */
|
|
|
static char *
|
static char *
|
parse_spr_params (args, group, index)
|
parse_spr_params (args, group, index)
|
char *args;
|
char *args;
|
int *group, *index;
|
int *group, *index;
|
{
|
{
|
| Line 939... |
Line 950... |
ptr_c++;
|
ptr_c++;
|
*ptr_c = 0;
|
*ptr_c = 0;
|
*index = (int) strtoul (args, &ptr_c, 0);
|
*index = (int) strtoul (args, &ptr_c, 0);
|
if (*ptr_c != 0)
|
if (*ptr_c != 0)
|
*index = or1k_regno_from_name (*group, args);
|
*index = or1k_regno_from_name (*group, args);
|
|
else *index = -1;
|
|
|
if (*index < 0)
|
if (*index < 0)
|
{
|
{
|
|
printf_filtered ("No register supplied. Valid registers are:\n");
|
for (i = 0; i < or1k_spr_valid_aliases[*group]; i++)
|
for (i = 0; i < or1k_spr_valid_aliases[*group]; i++)
|
printf_unfiltered ("%s\t", or1k_spr_register_name (SPR_REG(*group, i)));
|
{
|
printf_unfiltered ("\n");
|
char reg_name[16];
|
|
char *gen_name = or1k_spr_register_name (SPR_REG(*group, i));
|
|
sprintf (reg_name, "SPR%i_%i", *group, i);
|
|
if (strcmp (reg_name, gen_name) != 0)
|
|
printf_filtered ("%s\t", gen_name);
|
|
}
|
|
printf_filtered ("\n");
|
return args + strlen(args) + 1;
|
return args + strlen(args) + 1;
|
}
|
}
|
}
|
}
|
}
|
}
|
else
|
else
|
/* No parameters - print groups */
|
/* No parameters - print groups */
|
{
|
{
|
int i;
|
int i;
|
printf_unfiltered ("No parameter supplied. Valid groups are:\n");
|
printf_filtered ("No parameter supplied. Valid groups are:\n");
|
for (i = 0; i < OR1K_NUM_SPR_GROUPS; i++)
|
for (i = 0; i < OR1K_NUM_SPR_GROUPS; i++)
|
printf_unfiltered ("%s\t", or1k_group_names[i]);
|
printf_filtered ("%s\t", or1k_group_names[i]);
|
printf_unfiltered ("\nSingle register name or register name or number after the group can be also supplied.\n");
|
printf_filtered ("\nSingle register name or register name or number after the group can be also supplied.\n");
|
|
return args;
|
}
|
}
|
return args + strlen(args) + 1;
|
return args + strlen(args) + 1;
|
}
|
}
|
|
|
/* SPR register info. */
|
/* SPR register info. */
|
| Line 983... |
Line 1003... |
void
|
void
|
spr_command (char *args, int from_tty)
|
spr_command (char *args, int from_tty)
|
{
|
{
|
int group, index;
|
int group, index;
|
char *nargs = parse_spr_params (args, &group, &index);
|
char *nargs = parse_spr_params (args, &group, &index);
|
/* Any arguments left? */
|
|
if (args + strlen(args) >= nargs)
|
|
error ("Invalid register value.");
|
|
if (index >= 0)
|
if (index >= 0)
|
{
|
{
|
unsigned long prev;
|
unsigned long prev;
|
unsigned long value;
|
unsigned long value;
|
char *ptr_c;
|
char *ptr_c;
|
|
|
|
/* Any arguments left? */
|
|
if (args + strlen(args) >= nargs)
|
|
error ("Invalid register value.");
|
|
|
prev = or1k_read_spr_reg (SPR_REG(group, index));
|
prev = or1k_read_spr_reg (SPR_REG(group, index));
|
|
|
ptr_c = nargs;
|
ptr_c = nargs;
|
while (*ptr_c != ' ' && *ptr_c != 0)
|
while (*ptr_c != ' ' && *ptr_c != 0)
|
ptr_c++;
|
ptr_c++;
|
