| Line 40... |
Line 40... |
|
|
/* *INDENT-OFF* */
|
/* *INDENT-OFF* */
|
|
|
/* Group reg name size. See or1k_reg_names. */
|
/* Group reg name size. See or1k_reg_names. */
|
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = {
|
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = {
|
80, 0, 0, 6, 4, 2,
|
72, 0, 0, 6, 4, 2,
|
23, 16, 1, 3, 2, 8};
|
22, 16, 1, 3, 2, 8};
|
|
|
int or1k_group_name_start[OR1K_NUM_SPR_GROUPS] = {
|
int or1k_group_name_start[OR1K_NUM_SPR_GROUPS] = {
|
0, 0, 0, 253, 254, 256,
|
0, 0, 0, 253, 254, 256,
|
32, 248, 16, 16, 255, 0};
|
16, 248, 16, 16, 255, 0};
|
|
|
/* Generated reg names (max valid alias index).
|
/* Generated reg names (max valid alias index).
|
See or1k_spr_reg_name. */
|
See or1k_spr_reg_name. */
|
int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = {
|
int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = {
|
2047+1, 2047+1, 2047+1, 258+1, 257+1, 257+1,
|
2047+1, 2047+1, 2047+1, 258+1, 257+1, 257+1,
|
79+1, 263+1, 16+1, 18+1, 256+1, 7+1};
|
78+1, 263+1, 16+1, 18+1, 256+1, 7+1};
|
|
|
/* Register names. */
|
/* Register names. */
|
char *or1k_reg_names[] = {
|
char *or1k_reg_names[] = {
|
|
|
/* group 0 - general*/
|
/* group 0 - general*/
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| Line 83... |
Line 83... |
"MACLO", "MACHI",
|
"MACLO", "MACHI",
|
|
|
/* group 6 - debug */
|
/* group 6 - debug */
|
"DVR0", "DVR1", "DVR2", "DVR3", "DVR4", "DVR5", "DVR6", "DVR7",
|
"DVR0", "DVR1", "DVR2", "DVR3", "DVR4", "DVR5", "DVR6", "DVR7",
|
"DCR0", "DCR1", "DCR2", "DCR3", "DCR4", "DCR5", "DCR6", "DCR7",
|
"DCR0", "DCR1", "DCR2", "DCR3", "DCR4", "DCR5", "DCR6", "DCR7",
|
"DMR1", "DMR2", "DCWR0","DCWR1","DSR", "DRR", "DIR",
|
"DMR1", "DMR2", "DCWR0","DCWR1","DSR", "DRR",
|
|
|
/* group 7 - performance counters unit */
|
/* group 7 - performance counters unit */
|
"PCCM0", "PCMR1", "PCMR2", "PCMR3", "PCMR4", "PCMR5", "PCMR6", "PCMR7",
|
"PCCM0", "PCMR1", "PCMR2", "PCMR3", "PCMR4", "PCMR5", "PCMR6", "PCMR7",
|
"PCCR0", "PCCR1", "PCCR2", "PCCR3", "PCCR4", "PCCR5", "PCCR6", "PCCR7",
|
"PCCR0", "PCCR1", "PCCR2", "PCCR3", "PCCR4", "PCCR5", "PCCR6", "PCCR7",
|
|
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| Line 105... |
Line 105... |
};
|
};
|
|
|
static char *or1k_gdb_reg_names[] = {
|
static char *or1k_gdb_reg_names[] = {
|
|
|
/* general purpose registers */
|
/* general purpose registers */
|
"ZERO", "SP", "FP", "A0", "A1", "A2", "A3", "A4",
|
"R0", "R1(SP)", "R2(FP)", "R3(A0)", "R4(A1)", "R5(A2)", "R6(A3)", "R7(A4)",
|
"A5", "LR", "R10", "RV", "R12", "R13", "R14", "R15",
|
"R8(A5)", "R9(LR)", "R10", "R11(RV)", "R12", "R13", "R14", "R15",
|
"R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
|
"R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
|
"R24", "R25", "R26", "R27", "R28", "R29", "R30", "R31",
|
"R24", "R25", "R26", "R27", "R28", "R29", "R30", "R31",
|
|
|
/* Modified by CZ 12/09/01 */
|
/* Modified by CZ 12/09/01 */
|
/* vector/floating point registers */
|
/* vector/floating point registers */
|
| Line 346... |
Line 346... |
|
|
switch(regno)
|
switch(regno)
|
{
|
{
|
case PS_REGNUM: return SR_SPRNUM;
|
case PS_REGNUM: return SR_SPRNUM;
|
case PC_REGNUM: return PC_SPRNUM;
|
case PC_REGNUM: return PC_SPRNUM;
|
case CCR_REGNUM: return CCR_SPRNUM(CURRENT_CID);
|
/*case CCR_REGNUM: return CCR_SPRNUM(CURRENT_CID);*/
|
case EPC_REGNUM: return EPC_SPRNUM(CURRENT_CID);
|
case EPCR_REGNUM: return EPCR_SPRNUM(CURRENT_CID);
|
case EAR_REGNUM: return EAR_SPRNUM(CURRENT_CID);
|
/*case EAR_REGNUM: return EAR_SPRNUM(CURRENT_CID);
|
case ESR_REGNUM: return ESR_SPRNUM(CURRENT_CID);
|
case ESR_REGNUM: return ESR_SPRNUM(CURRENT_CID);*/
|
default:
|
default:
|
error("Invalid register number!");
|
error("Invalid register number!");
|
break;
|
break;
|
}
|
}
|
|
|
| Line 394... |
Line 394... |
{
|
{
|
int group_start = 0;
|
int group_start = 0;
|
for (i = 0; i < group; i++)
|
for (i = 0; i < group; i++)
|
group_start += or1k_group_name_sizes[i];
|
group_start += or1k_group_name_sizes[i];
|
|
|
|
index -= or1k_group_name_start[group];
|
if (index >= or1k_group_name_sizes[group])
|
if (index >= or1k_group_name_sizes[group])
|
{
|
{
|
sprintf (tmp_name, "SPR%i_%i", group, index);
|
sprintf (tmp_name, "SPR%i_%i", group, index);
|
return (char *)&tmp_name;
|
return (char *)&tmp_name;
|
}
|
}
|
else
|
else
|
return or1k_reg_names[group_start + index - or1k_group_name_start[group]];
|
return or1k_reg_names[group_start + index];
|
}
|
}
|
|
|
/* Build names for DMMU group. */
|
/* Build names for DMMU group. */
|
case 1:
|
case 1:
|
case 2:
|
case 2:
|
| Line 467... |
Line 468... |
i = (int) strtoul (name, &ptr_c, 10);
|
i = (int) strtoul (name, &ptr_c, 10);
|
if (*ptr_c)
|
if (*ptr_c)
|
return -1;
|
return -1;
|
else return i;
|
else return i;
|
}
|
}
|
for (i = 0; i < or1k_spr_valid_aliases[group]; i++)
|
for (i = or1k_group_name_start[group]; i < or1k_spr_valid_aliases[group]; i++)
|
{
|
{
|
char *s;
|
char *s;
|
s = or1k_spr_register_name (SPR_REG(group, i));
|
s = or1k_spr_register_name (SPR_REG(group, i));
|
if (strcasecmp (name, s) == 0)
|
if (strcasecmp (name, s) == 0)
|
return i;
|
return i;
|
| Line 869... |
Line 870... |
static const int MAX_PROLOGUE_LENGTH = 21;
|
static const int MAX_PROLOGUE_LENGTH = 21;
|
|
|
for (i = 0; i < MAX_GPR_REGS; i++)
|
for (i = 0; i < MAX_GPR_REGS; i++)
|
or1k_saved_reg_addr[i] = -1;
|
or1k_saved_reg_addr[i] = -1;
|
|
|
for(t_pc=pc; t_pc < (pc + MAX_PROLOGUE_LENGTH) &&
|
/* Is there a prologue? */
|
state != PrologueStateMachineInvalid; t_pc += OR1K_INSTLEN)
|
inst = or1k_fetch_instruction (pc);
|
{
|
if ((inst & 0xfc1ff800) != 0xd4011000) return pc; /* l.sw I(r1),r2 */
|
unsigned long insn = or1k_fetch_instruction(t_pc);
|
or1k_saved_reg_addr[2] = offset++;
|
int reg;
|
inst = or1k_fetch_instruction (pc + OR1K_INSTLEN);
|
int offset;
|
if ((inst & 0xFFFF0000) != 0x9c410000) return pc; /* l.addi r2,r1,I */
|
FunctionPrologueStates new_state = getPrologueInsnType(insn,®,&offset);
|
pc += 2 * OR1K_INSTLEN;
|
|
inst = or1k_fetch_instruction (pc);
|
switch(state)
|
if ((inst & 0xFFFF0000) != 0x9c210000) return pc; /* l.addi r1,r1,I */
|
{
|
pc += OR1K_INSTLEN;
|
case PrologueStateMachineStart:
|
|
if(new_state == PrologueStateMachineFrameInitialized)
|
/* Skip stored registers. */
|
{
|
inst = or1k_fetch_instruction (pc);
|
frame_size = -offset;
|
while ((inst & 0xfc1ff800) != 0xd4020000) /* l.sw 0x0(r2),rx */
|
or1k_saved_reg_addr[1] = frame_size;
|
{
|
}
|
/* get saved reg. */
|
else
|
or1k_saved_reg_addr[(inst >> 11) & 0x1f] = offset++;
|
new_state = PrologueStateMachineInvalid;
|
pc += OR1K_INSTLEN;
|
break;
|
inst = or1k_fetch_instruction (pc);
|
case PrologueStateMachineFrameInitialized:
|
|
if(new_state == PrologueStateMachineFrameSaved)
|
|
or1k_saved_reg_addr[reg] = frame_size - offset;
|
|
else if(new_state == PrologueStateMachineRegisterSaved)
|
|
{
|
|
/* Ooops...we have a frameless function.
|
|
Not sure what this might mean, but
|
|
let's try and continue. */
|
|
or1k_saved_reg_addr[reg] = frame_size - offset;
|
|
}
|
|
else
|
|
new_state = PrologueStateMachineInvalid;
|
|
break;
|
|
case PrologueStateMachineFrameSaved:
|
|
if(new_state != PrologueStateMachineFrameAdjusted &&
|
|
offset != frame_size)
|
|
new_state = PrologueStateMachineInvalid;
|
|
break;
|
|
case PrologueStateMachineFrameAdjusted:
|
|
case PrologueStateMachineRegisterSaved:
|
|
if(new_state == PrologueStateMachineRegisterSaved)
|
|
or1k_saved_reg_addr[reg] = frame_size - offset;
|
|
else if(new_state == PrologueStateMachineParameterSaved)
|
|
or1k_saved_reg_addr[reg] = -offset;
|
|
else
|
|
new_state = PrologueStateMachineInvalid;
|
|
break;
|
|
case PrologueStateMachineParameterSaved:
|
|
if(new_state == PrologueStateMachineParameterSaved)
|
|
or1k_saved_reg_addr[reg] = -offset;
|
|
else
|
|
new_state = PrologueStateMachineInvalid;
|
|
break;
|
|
default:
|
|
new_state = PrologueStateMachineInvalid;
|
|
}
|
|
|
|
state = new_state;
|
|
}
|
}
|
|
|
return t_pc;
|
return t_pc;
|
}
|
}
|
|
|
| Line 1314... |
Line 1277... |
regno = or1k_regno_from_name (i, args);
|
regno = or1k_regno_from_name (i, args);
|
if (regno >= 0)
|
if (regno >= 0)
|
{
|
{
|
*group = i;
|
*group = i;
|
*index = regno;
|
*index = regno;
|
|
break;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
if (*group < 0 || *group >= OR1K_NUM_SPR_GROUPS)
|
if (*group < 0 || *group >= OR1K_NUM_SPR_GROUPS)
|
| Line 1339... |
Line 1303... |
{
|
{
|
printf_filtered ("No register supplied. Valid registers are:\n");
|
printf_filtered ("No register supplied. Valid registers are:\n");
|
for (i = 0; i < or1k_spr_valid_aliases[*group]; i++)
|
for (i = 0; i < or1k_spr_valid_aliases[*group]; i++)
|
{
|
{
|
char reg_name[16];
|
char reg_name[16];
|
char *gen_name = or1k_spr_register_name (SPR_REG(*group, i));
|
char *gen_name = or1k_spr_register_name (SPR_REG(*group, i + or1k_group_name_start[*group]));
|
sprintf (reg_name, "SPR%i_%i", *group, i);
|
sprintf (reg_name, "SPR%i_%i", *group, i);
|
if (strcmp (reg_name, gen_name) != 0)
|
if (strcmp (reg_name, gen_name) != 0)
|
printf_filtered ("%s\t", gen_name);
|
printf_filtered ("%s\t", gen_name);
|
}
|
}
|
printf_filtered ("\n");
|
printf_filtered ("\n");
|
| Line 1373... |
Line 1337... |
{
|
{
|
int group, index;
|
int group, index;
|
parse_spr_params (args, &group, &index);
|
parse_spr_params (args, &group, &index);
|
if (index >= 0)
|
if (index >= 0)
|
{
|
{
|
printf_unfiltered ("%s.%s (SPR%i_%i) set to %i(%X), was:%i(%X)\n", or1k_group_names[group],
|
unsigned long value = or1k_read_spr_reg (SPR_REG(group, index));
|
or1k_spr_register_name (SPR_REG(group, index)), group, index,
|
printf_unfiltered ("%s.%s = SPR%i_%i = %i(%x)\n", or1k_group_names[group],
|
or1k_read_spr_reg (SPR_REG(group, index)));
|
or1k_spr_register_name (SPR_REG(group, index)), group, index, value, value);
|
}
|
}
|
}
|
}
|
|
|
/* Set SPR register. */
|
/* Set SPR register. */
|
|
|
| Line 1407... |
Line 1371... |
ptr_c++;
|
ptr_c++;
|
*ptr_c = 0;
|
*ptr_c = 0;
|
value = strtoul (nargs, &ptr_c, 0);
|
value = strtoul (nargs, &ptr_c, 0);
|
if (*ptr_c != 0)
|
if (*ptr_c != 0)
|
error ("Invalid register value.");
|
error ("Invalid register value.");
|
printf_unfiltered ("%s.%s (SPR%i_%i) set to %i(%X), was:%i(%X)\n", or1k_group_names[group],
|
or1k_write_spr_reg (SPR_REG(group, index), value);
|
|
printf_unfiltered ("%s.%s (SPR%i_%i) set to %i(%x), was:%i(%x)\n", or1k_group_names[group],
|
or1k_spr_register_name (SPR_REG(group, index)), group, index,
|
or1k_spr_register_name (SPR_REG(group, index)), group, index,
|
value, value, prev, prev);
|
value, value, prev, prev);
|
}
|
}
|
}
|
}
|
|
|
