| Line 771... |
Line 771... |
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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dmr1 &= ~DMR1_ST;
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dmr1 &= ~DMR1_ST;
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|
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if (new_pc_set)
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if (new_pc_set)
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{
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{
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debug("resume: 1\n");
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or1k_write_spr_reg (PC_SPRNUM, pc);
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or1k_write_spr_reg (PC_SPRNUM, pc);
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new_pc_set = 0;
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new_pc_set = 0;
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}
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}
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else if (insn_has_delay_slot (ppc_insn) && (ppc != pc))
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else if (insn_has_delay_slot (ppc_insn) && (ppc != pc))
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{
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{
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/* Steping across delay slot insn - we have to reexcute branch insn */
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/* Steping across delay slot insn - we have to reexcute branch insn */
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debug("resume: 2\n");
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|
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if(breakpoint_here_p (ppc))
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if(breakpoint_here_p (ppc))
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or1k_write_mem(ppc, ppc_insn);
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or1k_write_mem(ppc, ppc_insn);
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|
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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| Line 790... |
Line 792... |
or1k_set_chain (SC_REGISTER);
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or1k_set_chain (SC_REGISTER);
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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do {
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do {
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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} while ((val & 1) == 0);
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} while ((val & 1) == 0);
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|
|
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new_pc_set = 0;
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}
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}
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else if (hit_breakpoint && ((ppc + 4) != npc))
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else if (hit_breakpoint && ((ppc + 4) != npc))
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{
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{
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debug("resume: 3\n");
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/* Trapped on delay slot instruction. */
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/* Trapped on delay slot instruction. */
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/* Set PC to branch insn preceding delay slot. */
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/* Set PC to branch insn preceding delay slot. */
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or1k_write_spr_reg (PC_SPRNUM, ppc - 4);
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or1k_write_spr_reg (PC_SPRNUM, ppc - 4);
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|
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or1k_unstall ();
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or1k_unstall ();
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| Line 804... |
Line 809... |
or1k_set_chain (SC_REGISTER);
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or1k_set_chain (SC_REGISTER);
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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do {
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do {
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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} while ((val & 1) == 0);
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} while ((val & 1) == 0);
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|
|
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new_pc_set = 0;
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}
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}
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else
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else
|
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{
|
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debug("resume: 4\n");
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or1k_write_spr_reg (PC_SPRNUM, pc);
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or1k_write_spr_reg (PC_SPRNUM, pc);
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|
|
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new_pc_set = 0;
|
|
}
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}
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}
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else
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else
|
{
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{
|
dmr1 &= ~DMR1_ST;
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dmr1 &= ~DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
|
|
if (new_pc_set)
|
if (new_pc_set)
|
{
|
{
|
|
debug("resume: 5\n");
|
or1k_write_spr_reg (PC_SPRNUM, pc);
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or1k_write_spr_reg (PC_SPRNUM, pc);
|
|
|
new_pc_set = 0;
|
new_pc_set = 0;
|
}
|
}
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else if (insn_has_delay_slot (ppc_insn) && !breakpoint_here_p (ppc))
|
else if (insn_has_delay_slot (ppc_insn) && !breakpoint_here_p (ppc))
|
|
{
|
|
debug("resume: 6\n");
|
or1k_write_spr_reg (PC_SPRNUM, ppc);
|
or1k_write_spr_reg (PC_SPRNUM, ppc);
|
|
|
|
new_pc_set = 0;
|
|
}
|
else if (insn_has_delay_slot (ppc_insn) && breakpoint_here_p (ppc))
|
else if (insn_has_delay_slot (ppc_insn) && breakpoint_here_p (ppc))
|
{
|
{
|
|
debug("resume: 7\n");
|
or1k_write_mem(ppc, ppc_insn);
|
or1k_write_mem(ppc, ppc_insn);
|
|
|
dmr1 |= DMR1_ST;
|
dmr1 |= DMR1_ST;
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
dmr1 &= ~DMR1_ST;
|
dmr1 &= ~DMR1_ST;
|
| Line 842... |
Line 861... |
} while ((val & 1) == 0);
|
} while ((val & 1) == 0);
|
|
|
or1k_write_mem(ppc, 0x21000001);
|
or1k_write_mem(ppc, 0x21000001);
|
|
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
|
|
|
new_pc_set = 0;
|
}
|
}
|
else
|
else
|
|
{
|
|
debug("resume: 8\n");
|
or1k_write_spr_reg (PC_SPRNUM, pc);
|
or1k_write_spr_reg (PC_SPRNUM, pc);
|
|
|
|
new_pc_set = 0;
|
|
}
|
}
|
}
|
|
|
/* We can now continue normally, independent of step */
|
/* We can now continue normally, independent of step */
|
or1k_unstall ();
|
or1k_unstall ();
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or1k_status = TARGET_RUNNING;
|
or1k_status = TARGET_RUNNING;
|
