| Line 43... |
Line 43... |
#define debug if (remote_debug) printf_unfiltered
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#define debug if (remote_debug) printf_unfiltered
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/* The following prototype is necessary or the compiler will not
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/* The following prototype is necessary or the compiler will not
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correctly promote the data argument to ULONGEST */
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correctly promote the data argument to ULONGEST */
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static void or1k_write_reg (unsigned int, ULONGEST);
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static void or1k_write_reg (unsigned int, ULONGEST);
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static int insn_has_delay_slot (unsigned int);
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static int insn_modifies_gprs (unsigned int insn);
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/* JTAG or1k target ops. */
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/* JTAG or1k target ops. */
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extern void jtag_init PARAMS ((char * args));
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extern void jtag_init PARAMS ((char * args));
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extern ULONGEST jtag_read_reg PARAMS ((unsigned int regno));
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extern ULONGEST jtag_read_reg PARAMS ((unsigned int regno));
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extern void jtag_write_reg PARAMS ((unsigned int regno, ULONGEST data));
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extern void jtag_write_reg PARAMS ((unsigned int regno, ULONGEST data));
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| Line 159... |
Line 159... |
static int interrupt_count = 0;
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static int interrupt_count = 0;
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/* Reason of last stop. */
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/* Reason of last stop. */
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static int hit_watchpoint = 0;
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static int hit_watchpoint = 0;
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static int hit_breakpoint = 0;
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static int hit_breakpoint = 0;
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static int step_link_insn = 0;
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static int new_pc_set = 0;
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static int new_pc_set = 0;
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/* Current register values. */
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/* Current register values. */
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unsigned int dmr1 = 0;
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unsigned int dmr1 = 0;
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unsigned int dmr2 = 0;
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unsigned int dmr2 = 0;
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unsigned int dsr = 0;
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unsigned int dsr = 0;
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unsigned int drr = 0;
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unsigned int drr = 0;
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unsigned int lr = 0;
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/* Current matchpoints. */
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/* Current matchpoints. */
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unsigned int dvr[MAX_MATCHPOINTS];
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unsigned int dvr[MAX_MATCHPOINTS];
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struct dcr_struct dcr[MAX_MATCHPOINTS];
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struct dcr_struct dcr[MAX_MATCHPOINTS];
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| Line 297... |
Line 299... |
{
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{
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or1k_set_chain (SC_RISC_DEBUG);
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or1k_set_chain (SC_RISC_DEBUG);
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or1k_write_reg (regno, (ULONGEST)data);
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or1k_write_reg (regno, (ULONGEST)data);
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if (regno == PC_SPRNUM) {
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if (regno == PC_SPRNUM) {
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hit_breakpoint = 0;
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hit_breakpoint = 0;
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step_link_insn = 0;
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new_pc_set = 1;
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new_pc_set = 1;
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}
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}
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}
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}
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/* Reads register SPR from regno. */
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/* Reads register SPR from regno. */
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| Line 516... |
Line 519... |
memset (&or1k_htrace, 0, sizeof (or1k_htrace));
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memset (&or1k_htrace, 0, sizeof (or1k_htrace));
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/* RECSELDEPEND = 0 does not match our trace scheme. */
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/* RECSELDEPEND = 0 does not match our trace scheme. */
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or1k_htrace.moder.rec_sel_dep = 1;
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or1k_htrace.moder.rec_sel_dep = 1;
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debug_regs_changed = 1;
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debug_regs_changed = 0;//1;
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or1k_commit_debug_registers ();
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or1k_commit_debug_registers ();
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if (err != 0)
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if (err != 0)
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error ("Cannot connect.");
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error ("Cannot connect.");
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| Line 741... |
Line 744... |
unsigned int pc;
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unsigned int pc;
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unsigned int ppc;
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unsigned int ppc;
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unsigned int npc;
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unsigned int npc;
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unsigned int val;
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unsigned int val;
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unsigned int ppc_insn;
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unsigned int ppc_insn;
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unsigned int pc_insn;
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pc = read_pc();
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pc = read_pc();
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npc = or1k_read_spr_reg (PC_SPRNUM);
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npc = or1k_read_spr_reg (PC_SPRNUM);
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ppc = or1k_read_spr_reg (PPC_SPRNUM);
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ppc = or1k_read_spr_reg (PPC_SPRNUM);
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debug ("pc = %08x BP = %x npc = %08x ppc = %08x\n", pc, breakpoint_here_p (pc), npc, ppc);
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debug ("pc = %08x BP = %x npc = %08x ppc = %08x\n", pc, breakpoint_here_p (pc), npc, ppc);
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| Line 759... |
Line 763... |
/* Clear reason register for later. */
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/* Clear reason register for later. */
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or1k_write_spr_reg (DRR_SPRNUM, 0);
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or1k_write_spr_reg (DRR_SPRNUM, 0);
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or1k_commit_debug_registers ();
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or1k_commit_debug_registers ();
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/* Fetch previous insn */
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ppc_insn = or1k_fetch_instruction(ppc);
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ppc_insn = or1k_fetch_instruction(ppc);
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/* Else clause added by CZ 26/06/01 */
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/* Fetch next insn */
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pc_insn = or1k_fetch_instruction (pc);
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if (step)
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if (step)
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{
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{
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/* HW STEP. Set DMR1_ST. */
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/* HW STEP. Set DMR1_ST. */
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dmr1 |= DMR1_ST;
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dmr1 |= DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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dmr1 &= ~DMR1_ST;
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dmr1 &= ~DMR1_ST;
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if (new_pc_set)
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if (new_pc_set)
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{
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{
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debug("resume: 1\n");
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debug("resume: 1\n");
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/* If new PC was set, then just set it again to fill the pipeline */
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or1k_write_spr_reg (PC_SPRNUM, pc);
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or1k_write_spr_reg (PC_SPRNUM, pc);
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new_pc_set = 0;
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if (is_delayed (pc_insn) && insn_modifies_gprs (pc_insn))
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{
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debug("resume: 10\n");
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/* We are steping across jump an link insn - save link
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register, so we will be able to restore it when we will
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step across delay slot insn */
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step_link_insn = 1;
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lr = or1k_read_spr_reg (REGNUM_TO_SPRNUM(9));
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}
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}
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else if (insn_has_delay_slot (ppc_insn) && (ppc != pc))
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}
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else if (is_delayed (ppc_insn) && (ppc != pc))
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{
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{
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/* Steping across delay slot insn - we have to reexcute branch insn */
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debug("resume: 2\n");
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debug("resume: 2\n");
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/* Steping across delay slot insn - we have to reexcute branch insn */
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if(breakpoint_here_p (ppc))
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if(breakpoint_here_p (ppc))
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or1k_write_mem(ppc, ppc_insn);
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or1k_write_mem(ppc, ppc_insn);
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if (insn_modifies_gprs (ppc_insn) && step_link_insn)
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{
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debug("resume: 11\n");
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/* If this is delay slot of jump an link insn that was
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allready executed - restore link register first */
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or1k_write_spr_reg (REGNUM_TO_SPRNUM(9), lr);
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step_link_insn = 0;
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}
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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or1k_unstall ();
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or1k_unstall ();
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or1k_set_chain (SC_REGISTER);
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or1k_set_chain (SC_REGISTER);
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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do {
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do {
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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} while ((val & 1) == 0);
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} while ((val & 1) == 0);
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new_pc_set = 0;
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}
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}
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else if (hit_breakpoint && ((ppc + 4) != npc))
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else if (hit_breakpoint && ((ppc + 4) != npc) && (pc != npc))
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{
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{
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debug("resume: 3\n");
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debug("resume: 3\n");
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/* Trapped on delay slot instruction. */
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/* Trapped on delay slot instruction. */
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/* Set PC to branch insn preceding delay slot. */
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/* Set PC to branch insn preceding delay slot. */
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or1k_write_spr_reg (PC_SPRNUM, ppc - 4);
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or1k_write_spr_reg (PC_SPRNUM, ppc - 4);
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if (insn_modifies_gprs (or1k_fetch_instruction (ppc - 4)))
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{
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debug("resume: 12\n");
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/* We are steping across jump an link insn - save link
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register, so we will be able to restore it when we will
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step across delay slot insn */
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step_link_insn = 1;
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lr = or1k_read_spr_reg (REGNUM_TO_SPRNUM(9));
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}
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or1k_unstall ();
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or1k_unstall ();
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or1k_set_chain (SC_REGISTER);
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or1k_set_chain (SC_REGISTER);
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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do {
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do {
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val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
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} while ((val & 1) == 0);
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} while ((val & 1) == 0);
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new_pc_set = 0;
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}
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}
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else
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else
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{
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{
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debug("resume: 4\n");
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debug("resume: 4\n");
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/* Steping across 'non delay slot' insn - set PC to fill the pipeline */
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or1k_write_spr_reg (PC_SPRNUM, pc);
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or1k_write_spr_reg (PC_SPRNUM, pc);
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new_pc_set = 0;
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if (is_delayed (pc_insn) && insn_modifies_gprs (pc_insn))
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{
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debug("resume: 13\n");
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/* We are steping across jump an link insn - save link
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register, so we will be able to restore it when we will
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step across delay slot insn */
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step_link_insn = 1;
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lr = or1k_read_spr_reg (REGNUM_TO_SPRNUM(9));
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}
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}
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}
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}
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}
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else
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else
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{
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{
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dmr1 &= ~DMR1_ST;
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dmr1 &= ~DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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if (new_pc_set)
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if (new_pc_set)
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{
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{
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debug("resume: 5\n");
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debug("resume: 5\n");
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or1k_write_spr_reg (PC_SPRNUM, pc);
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/* If new PC was set, then just set it again to fill the pipeline */
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new_pc_set = 0;
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step_link_insn = 0;
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or1k_write_spr_reg (PC_SPRNUM, pc);
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}
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}
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else if (insn_has_delay_slot (ppc_insn) && !breakpoint_here_p (ppc))
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else if (is_delayed (ppc_insn) && !breakpoint_here_p (ppc))
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{
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{
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debug("resume: 6\n");
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debug("resume: 6\n");
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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/* If next insn is delay slot insn - set PC to previous branch insn
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and continue from there to refill the pipeline */
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new_pc_set = 0;
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if (insn_modifies_gprs (ppc_insn) && step_link_insn)
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{
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debug("resume: 14\n");
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/* If this is delay slot of jump an link insn that was
|
|
allready executed - restore link register first */
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or1k_write_spr_reg (REGNUM_TO_SPRNUM(9), lr);
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step_link_insn = 0;
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}
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|
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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}
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}
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else if (insn_has_delay_slot (ppc_insn) && breakpoint_here_p (ppc))
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else if (is_delayed (ppc_insn) && breakpoint_here_p (ppc))
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{
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{
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debug("resume: 7\n");
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debug("resume: 7\n");
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/* If next insn is delay slot insn and previous branch insn
|
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is actually BP - replace BP with original branch insn, set PC
|
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to that insn step over it, put back BP and continue */
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or1k_write_mem(ppc, ppc_insn);
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or1k_write_mem(ppc, ppc_insn);
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dmr1 |= DMR1_ST;
|
dmr1 |= DMR1_ST;
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
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dmr1 &= ~DMR1_ST;
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dmr1 &= ~DMR1_ST;
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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or1k_write_spr_reg (PC_SPRNUM, ppc);
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if (insn_modifies_gprs (ppc_insn) && step_link_insn)
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{
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debug("resume: 15\n");
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/* If this is delay slot of jump an link insn that was
|
|
allready executed - restore link register first */
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or1k_write_spr_reg (REGNUM_TO_SPRNUM(9), lr);
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step_link_insn = 0;
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}
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or1k_unstall ();
|
or1k_unstall ();
|
|
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or1k_set_chain (SC_REGISTER);
|
or1k_set_chain (SC_REGISTER);
|
val = or1k_read_reg (JTAG_RISCOP);
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val = or1k_read_reg (JTAG_RISCOP);
|
do {
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do {
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| Line 861... |
Line 928... |
} while ((val & 1) == 0);
|
} while ((val & 1) == 0);
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|
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or1k_write_mem(ppc, 0x21000001);
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or1k_write_mem(ppc, 0x21000001);
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|
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
or1k_write_spr_reg (DMR1_SPRNUM, dmr1);
|
|
|
new_pc_set = 0;
|
|
}
|
}
|
else
|
else
|
{
|
{
|
debug("resume: 8\n");
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debug("resume: 8\n");
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or1k_write_spr_reg (PC_SPRNUM, pc);
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/* Continue from 'non delay slot' insn - set PC to fill the pipeline */
|
|
|
new_pc_set = 0;
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or1k_write_spr_reg (PC_SPRNUM, pc);
|
}
|
}
|
}
|
}
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|
|
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/* Now we are in normal program flow again */
|
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new_pc_set = 0;
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|
|
/* We can now continue normally, independent of step */
|
/* We can now continue normally, independent of step */
|
or1k_unstall ();
|
or1k_unstall ();
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or1k_status = TARGET_RUNNING;
|
or1k_status = TARGET_RUNNING;
|
debug ("-resume %i, %i, %i\n",step, siggnal, or1k_status);
|
debug ("-resume %i, %i, %i\n",step, siggnal, or1k_status);
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}
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}
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| Line 1826... |
Line 1894... |
if ((dmr2 >> (i + 11)) & 1)
|
if ((dmr2 >> (i + 11)) & 1)
|
printf_filtered (", increments counter");
|
printf_filtered (", increments counter");
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printf_filtered ("\n");
|
printf_filtered ("\n");
|
}
|
}
|
}
|
}
|
|
|
static int
|
static int
|
insn_has_delay_slot (insn)
|
insn_modifies_gprs(unsigned int insn)
|
unsigned int insn;
|
|
{
|
{
|
if (((insn >> 26) <= 4) || ((insn >> 26) == 17) || ((insn >> 26) == 18))
|
/* l.jal */
|
|
if ((insn >> 26) == 0x01)
|
return 1;
|
return 1;
|
else
|
|
|
/* l.jalr */
|
|
if ((insn >> 26) == 0x12)
|
|
return 1;
|
|
|
return 0;
|
return 0;
|
}
|
}
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|
|
void
|
void
|
_initialize_remote_or1k ()
|
_initialize_remote_or1k ()
|
