OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [insight/] [opcodes/] [or32.c] - Diff between revs 1656 and 1672

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1656 Rev 1672
Line 18... Line 18...
along with this program; if not, write to the Free Software
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 
/*
/*
 * $Log: not supported by cvs2svn $
 * $Log: not supported by cvs2svn $
 
 * Revision 1.51  2006/01/19 19:25:10  nogj
 
 * Pass the instruction operands as part of the op_queue structure.
 
 *
 * Revision 1.50  2005/11/18 18:15:21  nogj
 * Revision 1.50  2005/11/18 18:15:21  nogj
 * Execute l.ff1 instruction
 * Execute l.ff1 instruction
 *
 *
 * Revision 1.49  2005/11/06 16:23:07  nogj
 * Revision 1.49  2005/11/06 16:23:07  nogj
 * Fix parsing the destination register
 * Fix parsing the destination register
Line 511... Line 514...
{ "lf.sfle.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0,
{ "lf.sfle.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0,
  it_float },
  it_float },
{ "lf.cust1.d", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xE ----", EFI, 0,
{ "lf.cust1.d", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xE ----", EFI, 0,
  it_float },
  it_float },
 
 
{ "l.sd",      "I(rD),rB",     "11 0x4  IIIII DDDDD BBBB BIII IIII IIII", EFI,
{ "l.sd",      "I(rA),rB",     "11 0x4  IIIII AAAAA BBBB BIII IIII IIII", EFI,
  0, it_store },
  0, it_store },
{ "l.sw",      "I(rD),rB",     "11 0x5  IIIII DDDDD BBBB BIII IIII IIII",
{ "l.sw",      "I(rA),rB",     "11 0x5  IIIII AAAAA BBBB BIII IIII IIII",
  EF(l_sw), 0, it_store },
  EF(l_sw), 0, it_store },
{ "l.sb",      "I(rD),rB",     "11 0x6  IIIII DDDDD BBBB BIII IIII IIII",
{ "l.sb",      "I(rA),rB",     "11 0x6  IIIII AAAAA BBBB BIII IIII IIII",
  EF(l_sb), 0, it_store },
  EF(l_sb), 0, it_store },
{ "l.sh",      "I(rD),rB",     "11 0x7  IIIII DDDDD BBBB BIII IIII IIII",
{ "l.sh",      "I(rA),rB",     "11 0x7  IIIII AAAAA BBBB BIII IIII IIII",
  EF(l_sh), 0, it_store },
  EF(l_sh), 0, it_store },
 
 
{ "l.add",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0",
{ "l.add",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0",
  EF(l_add), OR32_W_FLAG, it_arith },
  EF(l_add), OR32_W_FLAG, it_arith },
{ "l.addc",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1",
{ "l.addc",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1",

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.