| Line 30... |
Line 30... |
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/* Dirty way to include inb and outb from, but they say it is
|
/* Dirty way to include inb and outb from, but they say it is
|
a standard one. */
|
a standard one. */
|
#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/system.h>
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#include "mc.h"
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|
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#define GDB_IN "../sim/rtl_sim/run/gdb_in.dat"
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#define GDB_IN "../sim/rtl_sim/run/gdb_in.dat"
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#define GDB_OUT "../sim/rtl_sim/run/gdb_out.dat"
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#define GDB_OUT "../sim/rtl_sim/run/gdb_out.dat"
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|
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/* Libraries for JTAG proxy server. */
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/* Libraries for JTAG proxy server. */
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| Line 71... |
Line 72... |
#define TMS_BIT (0x08) /* D0, pin #5 */
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#define TMS_BIT (0x08) /* D0, pin #5 */
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#define TDO_BIT (0x20) /* PE, pin #12 */
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#define TDO_BIT (0x20) /* PE, pin #12 */
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#define TMS (0x02)
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#define TMS (0x02)
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#define TDI (0x01)
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#define TDI (0x01)
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#else
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#else
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#ifdef XILINX
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#define TCLK_BIT (0x02) /* D1 pin 3 */
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#define TRST_BIT (0x10) /* Not used */
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#define TDI_BIT (0x01) /* D0 pin 2 */
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#define TMS_BIT (0x04) /* D2 pin 4 */
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#define TDO_BIT (0x10) /* S6 pin 13*/
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#define TMS (0x02)
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#define TDI (0x01)
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//#define TDO_INV
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#else
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#define TCLK_BIT (0x04) /* D2 pin 4 */
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#define TCLK_BIT (0x04) /* D2 pin 4 */
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#define TRST_BIT (0x08) /* D3 pin 5 */
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#define TRST_BIT (0x08) /* D3 pin 5 */
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#define TDI_BIT (0x10) /* D4 pin 6 */
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#define TDI_BIT (0x10) /* D4 pin 6 */
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#define TMS_BIT (0x20) /* D5 pin 7 */
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#define TMS_BIT (0x20) /* D5 pin 7 */
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#define TDO_BIT (0x20) /* S5 pin 12*/
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#define TDO_BIT (0x20) /* S5 pin 12*/
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#define TMS (0x02)
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#define TMS (0x02)
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#define TDI (0x01)
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#define TDI (0x01)
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#endif
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#endif
|
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#endif
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#ifdef RTL_SIM
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#ifdef RTL_SIM
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# define JTAG_WAIT() usleep(1000)
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# define JTAG_WAIT() usleep(1000)
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# define NUM_RETRIES (16)
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# define NUM_RETRIES (16)
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# define JTAG_RETRY_WAIT() usleep (1000)
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# define JTAG_RETRY_WAIT() usleep (1000)
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#else
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#else
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| Line 217... |
Line 229... |
inline static unsigned char
|
inline static unsigned char
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jp1_in () {
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jp1_in () {
|
int data;
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int data;
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#ifndef RTL_SIM
|
#ifndef RTL_SIM
|
data = inb (LPT_READ);
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data = inb (LPT_READ);
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#ifdef TDO_INV
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data = (data & TDO_BIT) != TDO_BIT;
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#else
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data = (data & TDO_BIT) == TDO_BIT;
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data = (data & TDO_BIT) == TDO_BIT;
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|
#endif
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#else
|
#else
|
FILE *fin = 0;
|
FILE *fin = 0;
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char ch;
|
char ch;
|
time_t time;
|
time_t time;
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struct stat s;
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struct stat s;
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| Line 346... |
Line 362... |
{
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{
|
int i;
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int i;
|
debug2 ("\nreset(");
|
debug2 ("\nreset(");
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jp1_out (0);
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jp1_out (0);
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JTAG_RETRY_WAIT();
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JTAG_RETRY_WAIT();
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/* In case we don't have TRST reset it manually */
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for (i = 0; i < 8; i++)
|
|
jp1_write_JTAG (TMS);
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jp1_out (TRST_BIT);
|
jp1_out (TRST_BIT);
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JTAG_RETRY_WAIT();
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JTAG_RETRY_WAIT();
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jp1_write_JTAG (0);
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jp1_write_JTAG (0);
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debug2(")\n");
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debug2(")\n");
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select_dr = 0;
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select_dr = 0;
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| Line 609... |
Line 628... |
jtag_write_reg (regno, data)
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jtag_write_reg (regno, data)
|
int regno;
|
int regno;
|
ULONGEST data;
|
ULONGEST data;
|
{
|
{
|
/* Set PC */
|
/* Set PC */
|
if (current_chain == SC_RISC_DEBUG && regno == 0x10)
|
// if (current_chain == SC_RISC_DEBUG && regno == 0x10)
|
data = data - 4;
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// data = data - 4;
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|
|
jtag_write_reg_support (regno, data);
|
jtag_write_reg_support (regno, data);
|
}
|
}
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|
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/* Stalls the CPU. */
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/* Stalls the CPU. */
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| Line 647... |
Line 666... |
jtag_init () {
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jtag_init () {
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int tmp, i;
|
int tmp, i;
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unsigned int npc, ppc, r1, insn, result;
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unsigned int npc, ppc, r1, insn, result;
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current_chain = -1;
|
current_chain = -1;
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jp1_reset_JTAG ();
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jp1_reset_JTAG ();
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#if 0
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#define MC_BASE_ADD 0x60000000
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#define MC_CSR_VAL 0x04300300
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#define MC_MASK_VAL 0x000000ff
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#define FLASH_BASE_ADD 0x04000000
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#define FLASH_TMS_VAL 0x0010a10a
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#define SDRAM_BASE_ADD 0x00000000
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#define SDRAM_TMS_VAL 0x07248230
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jtag_set_chain (SC_REGISTER);
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jtag_write_reg (4, 0x00000001);
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jtag_set_chain (SC_WISHBONE);
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jtag_write_reg (MC_BASE_ADD + MC_CSC(0), (((FLASH_BASE_ADD & 0xffff0000) >> 5) | 0x25));
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jtag_write_reg (MC_BASE_ADD + MC_TMS(0), FLASH_TMS_VAL);
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jtag_write_reg (MC_BASE_ADD + MC_BA_MASK, MC_MASK_VAL);
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jtag_write_reg (MC_BASE_ADD + MC_CSR, MC_CSR_VAL);
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jtag_write_reg (MC_BASE_ADD + MC_TMS(1), SDRAM_TMS_VAL);
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jtag_write_reg (MC_BASE_ADD + MC_CSC(1), (((SDRAM_BASE_ADD & 0xffff0000) >> 5) | 0x0411));
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sleep(1);
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#endif
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#if 1
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#if 1
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|
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#define RAM_BASE 0x40000000
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#define RAM_BASE 0x00000000
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/* Stall risc */
|
/* Stall risc */
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jtag_set_chain (SC_REGISTER);
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jtag_set_chain (SC_REGISTER);
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jtag_write_reg (4, 0x00000001);
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jtag_write_reg (4, 0x00000001);
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|
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jtag_set_chain (SC_WISHBONE);
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jtag_set_chain (SC_WISHBONE);
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| Line 708... |
Line 751... |
/* Read R1 */
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/* Read R1 */
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jtag_set_chain (SC_RISC_DEBUG);
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jtag_set_chain (SC_RISC_DEBUG);
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r1 = jtag_read_reg (0x401);
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r1 = jtag_read_reg (0x401);
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r1 = jtag_read_reg (0x401);
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r1 = jtag_read_reg (0x401);
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printf("npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
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printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
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printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x4000000c, 0x40000024, 5);
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result = npc + ppc + r1;
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result = npc + ppc + r1;
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|
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/* Reset step bit */
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/* Reset step bit */
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jtag_set_chain (SC_RISC_DEBUG);
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jtag_set_chain (SC_RISC_DEBUG);
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| Line 748... |
Line 792... |
|
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/* Set back original insn */
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/* Set back original insn */
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jtag_set_chain (SC_WISHBONE);
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jtag_set_chain (SC_WISHBONE);
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jtag_write_reg (RAM_BASE + 0x24, insn);
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jtag_write_reg (RAM_BASE + 0x24, insn);
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printf("npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
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printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
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printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x4000000c, 0x40000024, 8);
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result = npc + ppc + r1 + result;
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result = npc + ppc + r1 + result;
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|
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|
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/* Set trap insn in place of branch insn */
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/* Set trap insn in place of branch insn */
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jtag_set_chain (SC_WISHBONE);
|
jtag_set_chain (SC_WISHBONE);
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| Line 786... |
Line 831... |
|
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/* Set back original insn */
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/* Set back original insn */
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jtag_set_chain (SC_WISHBONE);
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jtag_set_chain (SC_WISHBONE);
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jtag_write_reg (RAM_BASE + 0x20, insn);
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jtag_write_reg (RAM_BASE + 0x20, insn);
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|
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printf("npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
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printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
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printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000024, 0x40000020, 11);
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result = npc + ppc + r1 + result;
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result = npc + ppc + r1 + result;
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|
|
|
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/* Set trap insn before branch insn */
|
/* Set trap insn before branch insn */
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jtag_set_chain (SC_WISHBONE);
|
jtag_set_chain (SC_WISHBONE);
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| Line 824... |
Line 870... |
|
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/* Set back original insn */
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/* Set back original insn */
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jtag_set_chain (SC_WISHBONE);
|
jtag_set_chain (SC_WISHBONE);
|
jtag_write_reg (RAM_BASE + 0x1c, insn);
|
jtag_write_reg (RAM_BASE + 0x1c, insn);
|
|
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printf("npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000020, 0x4000001c, 24);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
|
|
/* Set trap insn behind lsu insn */
|
/* Set trap insn behind lsu insn */
|
jtag_set_chain (SC_WISHBONE);
|
jtag_set_chain (SC_WISHBONE);
|
| Line 862... |
Line 909... |
|
|
/* Set back original insn */
|
/* Set back original insn */
|
jtag_set_chain (SC_WISHBONE);
|
jtag_set_chain (SC_WISHBONE);
|
jtag_write_reg (RAM_BASE + 0x18, insn);
|
jtag_write_reg (RAM_BASE + 0x18, insn);
|
|
|
printf("npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x4000001c, 0x40000018, 49);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
/* Set trap insn very near previous one */
|
/* Set trap insn very near previous one */
|
jtag_set_chain (SC_WISHBONE);
|
jtag_set_chain (SC_WISHBONE);
|
insn = jtag_read_reg (RAM_BASE + 0x1c);
|
insn = jtag_read_reg (RAM_BASE + 0x1c);
|
| Line 899... |
Line 947... |
|
|
/* Set back original insn */
|
/* Set back original insn */
|
jtag_set_chain (SC_WISHBONE);
|
jtag_set_chain (SC_WISHBONE);
|
jtag_write_reg (RAM_BASE + 0x1c, insn);
|
jtag_write_reg (RAM_BASE + 0x1c, insn);
|
|
|
printf("npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000020, 0x4000001c, 50);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
|
|
/* Set trap insn to the start */
|
/* Set trap insn to the start */
|
jtag_set_chain (SC_WISHBONE);
|
jtag_set_chain (SC_WISHBONE);
|
| Line 937... |
Line 986... |
|
|
/* Set back original insn */
|
/* Set back original insn */
|
jtag_set_chain (SC_WISHBONE);
|
jtag_set_chain (SC_WISHBONE);
|
jtag_write_reg (RAM_BASE + 0x0c, insn);
|
jtag_write_reg (RAM_BASE + 0x0c, insn);
|
|
|
printf("npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000010, 0x4000000c, 99);
|
|
result = npc + ppc + r1 + result;
|
|
|
|
|
|
/* Set step bit */
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
jtag_write_reg ((6 << 11) + 16, 1 << 22);
|
|
|
|
for (i = 0; i < 5; i++)
|
|
{
|
|
/* Unstall */
|
|
jtag_set_chain (SC_REGISTER);
|
|
jtag_write_reg (4, 0x00000000);
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
}
|
|
|
|
/* Read NPC */
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
npc = jtag_read_reg ((0 << 11) + 16);
|
|
npc = jtag_read_reg ((0 << 11) + 16);
|
|
|
|
/* Read PPC */
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
ppc = jtag_read_reg ((0 << 11) + 18);
|
|
ppc = jtag_read_reg ((0 << 11) + 18);
|
|
|
|
/* Read R1 */
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
r1 = jtag_read_reg (0x401);
|
|
r1 = jtag_read_reg (0x401);
|
|
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000024, 0x40000020, 101);
|
|
result = npc + ppc + r1 + result;
|
|
|
|
/* Set PC */
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
jtag_write_reg ((0 << 11) + 16, RAM_BASE + 0x20);
|
|
|
|
for (i = 0; i < 2; i++)
|
|
{
|
|
/* Unstall */
|
|
jtag_set_chain (SC_REGISTER);
|
|
jtag_write_reg (4, 0x00000000);
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
}
|
|
|
|
/* Read NPC */
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
npc = jtag_read_reg ((0 << 11) + 16);
|
|
npc = jtag_read_reg ((0 << 11) + 16);
|
|
|
|
/* Read PPC */
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
ppc = jtag_read_reg ((0 << 11) + 18);
|
|
ppc = jtag_read_reg ((0 << 11) + 18);
|
|
|
|
/* Read R1 */
|
|
jtag_set_chain (SC_RISC_DEBUG);
|
|
r1 = jtag_read_reg (0x401);
|
|
r1 = jtag_read_reg (0x401);
|
|
|
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x4000000c, 0x40000024, 201);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
printf("result = %.8lx\n", result + 0x5eaddc4b);
|
printf("result = %.8lx\n", result + 0x5eaddaa9);
|
|
|
#endif
|
#endif
|
|
|
return err;
|
return err;
|
}
|
}
|
