| Line 25... |
Line 25... |
#include <ctype.h>
|
#include <ctype.h>
|
#include <string.h>
|
#include <string.h>
|
#include <stdlib.h>
|
#include <stdlib.h>
|
#include <unistd.h>
|
#include <unistd.h>
|
#include <stdarg.h>
|
#include <stdarg.h>
|
|
#include <sys/stat.h>
|
|
#include <sys/types.h>
|
|
|
/* Dirty way to include inb and outb from, but they say it is
|
/* Dirty way to include inb and outb from, but they say it is
|
a standard one. */
|
a standard one. */
|
#include <asm/io.h>
|
#include <asm/io.h>
|
#include <asm/system.h>
|
#include <asm/system.h>
|
#include "mc.h"
|
#include "mc.h"
|
#include "gdb.h"
|
#include "gdb.h"
|
#include "jp2.h"
|
#include "jp2.h"
|
|
|
|
#define TC_RESET 0
|
|
#define TC_BRIGHT 1
|
|
#define TC_DIM 2
|
|
#define TC_UNDERLINE 3
|
|
#define TC_BLINK 4
|
|
#define TC_REVERSE 7
|
|
#define TC_HIDDEN 8
|
|
|
|
#define TC_BLACK 0
|
|
#define TC_RED 1
|
|
#define TC_GREEN 2
|
|
#define TC_YELLOW 3
|
|
#define TC_BLUE 4
|
|
#define TC_MAGENTA 5
|
|
#define TC_CYAN 6
|
|
#define TC_WHITE 7
|
|
|
static int base = 0x378; /* FIXME: We should detect the address. */
|
static int base = 0x378; /* FIXME: We should detect the address. */
|
int err = 0;
|
int err = 0;
|
int set_pc = 0;
|
int set_pc = 0;
|
int set_step = 0;
|
int set_step = 0;
|
int waiting = 0;
|
int waiting = 0;
|
| Line 91... |
Line 110... |
fclose(fout);
|
fclose(fout);
|
if(r == 0 || num_read !=(0x10 | value)) goto error;
|
if(r == 0 || num_read !=(0x10 | value)) goto error;
|
#else
|
#else
|
outb(value, LPT_WRITE);
|
outb(value, LPT_WRITE);
|
#endif /* RTL_SIM */
|
#endif /* RTL_SIM */
|
if (!(value & 1)) debug("[%x%c]",(value & TDI_BIT) != 0,(value & TMS_BIT)?'^':'_');
|
if (!(value & TCLK_BIT)) {
|
|
if (value & TMS_BIT) debug("%c[%d;%dm", 0x1b, TC_BRIGHT, TC_WHITE + 30);
|
|
debug("%x",(value & TDI_BIT) != 0);
|
|
debug("%c[%d;%dm", 0x1b, TC_RESET, TC_WHITE + 30);
|
|
}
|
flush_debug();
|
flush_debug();
|
}
|
}
|
|
|
/* Receive a byte from parallel port. */
|
/* Receive a byte from parallel port. */
|
inline static unsigned char jp2_in() {
|
inline static unsigned char jp2_in() {
|
| Line 122... |
Line 145... |
} else break;
|
} else break;
|
}
|
}
|
fclose(fin);
|
fclose(fin);
|
data = ch == '1';
|
data = ch == '1';
|
#endif /* !RTL_SIM */
|
#endif /* !RTL_SIM */
|
debug(" R%01X ", data);
|
debug("%c[%d;%dm", 0x1b, TC_BRIGHT, TC_GREEN + 30);
|
|
debug("%01X", data);
|
|
debug("%c[%d;%dm", 0x1b, TC_RESET, TC_WHITE + 30);
|
flush_debug();
|
flush_debug();
|
return data;
|
return data;
|
}
|
}
|
|
|
/* Writes TCLK=0, TRST=1, TMS=bit1, TDI=bit0
|
/* Writes TCLK=0, TRST=1, TMS=bit1, TDI=bit0
|
| Line 156... |
Line 181... |
/* Writes bitstream. LS bit first if len < 0, MS bit first if len > 0. */
|
/* Writes bitstream. LS bit first if len < 0, MS bit first if len > 0. */
|
static inline void jp2_write_stream(ULONGEST stream, int len, int set_last_bit) {
|
static inline void jp2_write_stream(ULONGEST stream, int len, int set_last_bit) {
|
int i;
|
int i;
|
if (len < 0) {
|
if (len < 0) {
|
len = -len;
|
len = -len;
|
debug("\nwriteL(");
|
debug("writeL%d(", len);
|
for(i = 0; i < len - 1; i++)
|
for(i = 0; i < len - 1; i++)
|
jp2_write_JTAG((stream >> i) & 1);
|
jp2_write_JTAG((stream >> i) & 1);
|
|
|
if(set_last_bit) jp2_write_JTAG((stream >>(len - 1))& 1 | TMS);
|
if(set_last_bit) jp2_write_JTAG((stream >>(len - 1))& 1 | TMS);
|
else jp2_write_JTAG((stream >>(len - 1))& 1);
|
else jp2_write_JTAG((stream >>(len - 1))& 1);
|
} else {
|
} else {
|
debug("\nwrite(");
|
debug("write%d(", len);
|
for(i = 0; i < len - 1; i++)
|
for(i = 0; i < len - 1; i++)
|
jp2_write_JTAG((stream >> (len - 1 - i)) & 1);
|
jp2_write_JTAG((stream >> (len - 1 - i)) & 1);
|
|
|
if(set_last_bit) jp2_write_JTAG((stream >> 0) & 1 | TMS);
|
if(set_last_bit) jp2_write_JTAG((stream >> 0) & 1 | TMS);
|
else jp2_write_JTAG((stream >> 0)& 1);
|
else jp2_write_JTAG((stream >> 0)& 1);
|
| Line 178... |
Line 203... |
/* Gets bitstream. LS bit first if len < 0, MS bit first if len > 0. */
|
/* Gets bitstream. LS bit first if len < 0, MS bit first if len > 0. */
|
inline static ULONGEST jp2_read_stream(unsigned long stream, int len, int set_last_bit) {
|
inline static ULONGEST jp2_read_stream(unsigned long stream, int len, int set_last_bit) {
|
int i;
|
int i;
|
ULONGEST data = 0;
|
ULONGEST data = 0;
|
if (len < 0) {
|
if (len < 0) {
|
debug("\nreadL(");
|
debug("readL(");
|
for(i = 0; i < len - 1; i++) {
|
for(i = 0; i < len - 1; i++) {
|
jp2_write_JTAG((stream >> i) & 1); /* LSB first */
|
jp2_write_JTAG((stream >> i) & 1); /* LSB first */
|
data |= jp2_read_JTAG() << i; /* LSB first */
|
data |= jp2_read_JTAG() << i; /* LSB first */
|
}
|
}
|
|
|
if (set_last_bit) jp2_write_JTAG((stream >> (len - 1)) & 1 | TMS);
|
if (set_last_bit) jp2_write_JTAG((stream >> (len - 1)) & 1 | TMS);
|
else jp2_write_JTAG((stream >> (len - 1)) & 1);
|
else jp2_write_JTAG((stream >> (len - 1)) & 1);
|
data |= jp2_read_JTAG() << (len - 1);
|
data |= jp2_read_JTAG() << (len - 1);
|
} else {
|
} else {
|
debug("\nread(");
|
debug("read(");
|
for(i = 0; i < len - 1; i++) {
|
for(i = 0; i < len - 1; i++) {
|
jp2_write_JTAG((stream >> (len - 1 - i)) & 1); /* MSB first */
|
jp2_write_JTAG((stream >> (len - 1 - i)) & 1); /* MSB first */
|
data |= jp2_read_JTAG() << (len - 1 - i); /* MSB first */
|
data |= jp2_read_JTAG() << (len - 1 - i); /* MSB first */
|
}
|
}
|
|
|
| Line 243... |
Line 268... |
/* select debug scan chain and stay in it forever */
|
/* select debug scan chain and stay in it forever */
|
jtag_set_ir(JI_DEBUG);
|
jtag_set_ir(JI_DEBUG);
|
current_chain = -1;
|
current_chain = -1;
|
return DBG_ERR_OK;
|
return DBG_ERR_OK;
|
}
|
}
|
|
/* counts retries and returns zero if we should abort */
|
/* counts retries and returns nonzero if we should abort */
|
|
/* TODO: dinamically adjust timings for jp2 */
|
/* TODO: dinamically adjust timings for jp2 */
|
static int retry_no = 0;
|
static int retry_no = 0;
|
int retry_do() {
|
int retry_do() {
|
int i, err;
|
int i, err;
|
|
printf("RETRY\n");
|
if (retry_no >= NUM_SOFT_RETRIES) {
|
if (retry_no >= NUM_SOFT_RETRIES) {
|
if ((err = dbg_reset())) return err;
|
if ((err = dbg_reset())) return err;
|
} else { /* quick reset */
|
} else { /* quick reset */
|
for(i = 0; i < 8; i++) jp2_write_JTAG(TMS);
|
for(i = 0; i < 8; i++) jp2_write_JTAG(TMS);
|
jp2_write_JTAG(0); /* go into IDLE state */
|
jp2_write_JTAG(0); /* go into IDLE state */
|
}
|
}
|
if (retry_no >= NUM_SOFT_RETRIES + NUM_HARD_RETRIES) {
|
if (retry_no >= NUM_SOFT_RETRIES + NUM_HARD_RETRIES) {
|
retry_no = 0;
|
retry_no = 0;
|
return 1;
|
return 0;
|
}
|
}
|
retry_no++;
|
retry_no++;
|
return DBG_ERR_OK;
|
return 1;
|
}
|
}
|
|
|
/* resets retry counter */
|
/* resets retry counter */
|
void retry_ok() {
|
void retry_ok() {
|
retry_no = 0;
|
retry_no = 0;
|
| Line 283... |
Line 308... |
jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
|
jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
|
jp2_write_JTAG(0); /* CAPTURE_DR */
|
jp2_write_JTAG(0); /* CAPTURE_DR */
|
jp2_write_JTAG(0); /* SHIFT_DR */
|
jp2_write_JTAG(0); /* SHIFT_DR */
|
|
|
/* write data, EXIT1_DR */
|
/* write data, EXIT1_DR */
|
crc_w = 0;
|
crc_w = 0xffffffff;
|
jp2_write_stream((chain & 0x7 | 0x8), DC_SIZE + 1, 0);
|
jp2_write_stream((chain & 0x7 | 0x8), DC_SIZE + 1, 0);
|
jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
|
jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
|
crc_r = 0;
|
crc_r = 0xffffffff;
|
status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
|
status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
|
crc_generated = crc_r;
|
crc_generated = crc_r;
|
crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
|
crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
|
|
|
/* invalid chain? */
|
/* invalid chain? */
|
| Line 310... |
Line 335... |
current_chain = chain;
|
current_chain = chain;
|
return DBG_ERR_OK;
|
return DBG_ERR_OK;
|
}
|
}
|
|
|
/* sends out a command with 32bit address and 16bit length, if len >= 0 */
|
/* sends out a command with 32bit address and 16bit length, if len >= 0 */
|
int dbg_command(unsigned long adr, int command, int len) {
|
int dbg_command(unsigned long adr, int command, int expect_status, int len) {
|
int status, crc_generated, crc_read;
|
int status, crc_generated, crc_read;
|
|
|
try_again:
|
try_again:
|
dbg_set_chain(dbg_chain);
|
dbg_set_chain(dbg_chain);
|
debug("\n");
|
debug("\n");
|
| Line 324... |
Line 349... |
jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
|
jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
|
jp2_write_JTAG(0); /* CAPTURE_DR */
|
jp2_write_JTAG(0); /* CAPTURE_DR */
|
jp2_write_JTAG(0); /* SHIFT_DR */
|
jp2_write_JTAG(0); /* SHIFT_DR */
|
|
|
/* write data, EXIT1_DR */
|
/* write data, EXIT1_DR */
|
crc_w = 0;
|
crc_w = 0xffffffff;
|
jp2_write_stream((command & 0x7), DC_SIZE + 1, 0);
|
jp2_write_stream((command & 0x7), DC_SIZE + 1, 0);
|
jp2_write_stream(adr, 32, 0);
|
jp2_write_stream(adr, 32, 0);
|
if (len >= 0) jp2_write_stream(len, 16, 0);
|
if (len >= 0) jp2_write_stream(len, 16, 0);
|
jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
|
jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
|
crc_r = 0;
|
crc_r = 0xffffffff;
|
status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
|
status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
|
crc_generated = crc_r;
|
crc_generated = crc_r;
|
crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
|
crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
|
|
|
/* we should read 1000, otherwise retry */
|
/* we should read expected status value, otherwise retry */
|
if (status != 0x8 || crc_read != crc_generated) {
|
if (status != expect_status || crc_read != crc_generated) {
|
if (retry_do()) goto try_again;
|
if (retry_do()) goto try_again;
|
else return DBG_ERR_CRC;
|
else return DBG_ERR_CRC;
|
}
|
}
|
jp2_write_JTAG(TMS); /* UPDATE_DR */
|
jp2_write_JTAG(TMS); /* UPDATE_DR */
|
jp2_write_JTAG(0); /* IDLE */
|
jp2_write_JTAG(0); /* IDLE */
|
| Line 348... |
Line 373... |
retry_ok();
|
retry_ok();
|
return DBG_ERR_OK;
|
return DBG_ERR_OK;
|
}
|
}
|
|
|
/* issues a burst read/write */
|
/* issues a burst read/write */
|
int dbg_go(int go_command, unsigned char *data, unsigned short len, int read) {
|
int dbg_go(int go_command, unsigned char *data, unsigned short len, int read, int expected_status) {
|
int status, crc_generated, crc_read;
|
int status, crc_generated, crc_read;
|
int i;
|
int i;
|
|
|
try_again:
|
try_again:
|
dbg_set_chain(dbg_chain);
|
dbg_set_chain(dbg_chain);
|
| Line 362... |
Line 387... |
jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
|
jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
|
jp2_write_JTAG(0); /* CAPTURE_DR */
|
jp2_write_JTAG(0); /* CAPTURE_DR */
|
jp2_write_JTAG(0); /* SHIFT_DR */
|
jp2_write_JTAG(0); /* SHIFT_DR */
|
|
|
/* write data, EXIT1_DR */
|
/* write data, EXIT1_DR */
|
crc_w = 0;
|
crc_w = 0xffffffff;
|
jp2_write_stream(go_command, DC_SIZE + 1, 0);
|
jp2_write_stream(go_command, DC_SIZE + 1, 0);
|
|
if (!read) {
|
|
/* reverse byte ordering, since we must send in big endian */
|
for (i = 0; i < len; i++)
|
for (i = 0; i < len; i++)
|
if (read) data[i] = jp2_read_stream(data[i], 8, 0);
|
jp2_write_stream(data[i], 8, 0);
|
else jp2_write_stream(data[i], 8, 0);
|
}
|
jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
|
jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
|
crc_r = 0;
|
crc_r = 0xffffffff;
|
|
if (read) {
|
|
/* reverse byte ordering, since we must send in big endian */
|
|
for (i = 0; i < len; i++)
|
|
data[i] = jp2_read_stream(data[i], 8, 0);
|
|
}
|
status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
|
status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
|
crc_generated = crc_r;
|
crc_generated = crc_r;
|
crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
|
crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
|
|
|
/* was there an bus error */
|
/* was there an bus error -- wishbone only */
|
if (status == 0x9 || crc_read == crc_generated) return DBG_ERR_BUSERR;
|
if (status == 0x9 && crc_read == crc_generated) return DBG_ERR_BUSERR;
|
|
//printf("[status %x %x %x %x]\n", status, expected_status, crc_read, crc_generated);
|
|
|
/* we should read 1000, otherwise retry */
|
/* we should read expected status, otherwise retry */
|
if (status != 0x8 || crc_read != crc_generated) {
|
if (status != expected_status || crc_read != crc_generated) {
|
if (retry_do()) goto try_again;
|
if (retry_do()) goto try_again;
|
else return DBG_ERR_CRC;
|
else return DBG_ERR_CRC;
|
}
|
}
|
jp2_write_JTAG(TMS); /* UPDATE_DR */
|
jp2_write_JTAG(TMS); /* UPDATE_DR */
|
jp2_write_JTAG(0); /* IDLE */
|
jp2_write_JTAG(0); /* IDLE */
|
| Line 404... |
Line 437... |
jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
|
jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
|
jp2_write_JTAG(0); /* CAPTURE_DR */
|
jp2_write_JTAG(0); /* CAPTURE_DR */
|
jp2_write_JTAG(0); /* SHIFT_DR */
|
jp2_write_JTAG(0); /* SHIFT_DR */
|
|
|
/* write data, EXIT1_DR */
|
/* write data, EXIT1_DR */
|
crc_w = 0;
|
crc_w = 0xffffffff;
|
jp2_write_stream(DI_WB_STATUS, DC_SIZE + 1, 0);
|
jp2_write_stream(DI_WB_STATUS, DC_SIZE + 1, 0);
|
jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
|
jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
|
crc_r = 0;
|
crc_r = 0xffffffff;
|
status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
|
status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
|
crc_generated = crc_r;
|
crc_generated = crc_r;
|
crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
|
crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
|
|
|
/* is cycle still in progress */
|
/* is cycle still in progress */
|
| Line 439... |
Line 472... |
|
|
/* read a block from wishbone */
|
/* read a block from wishbone */
|
int dbg_wb_read(unsigned long adr, int command, unsigned char *data, unsigned short len) {
|
int dbg_wb_read(unsigned long adr, int command, unsigned char *data, unsigned short len) {
|
int err;
|
int err;
|
if ((err = dbg_set_chain(DC_WISHBONE))) return err;
|
if ((err = dbg_set_chain(DC_WISHBONE))) return err;
|
if ((err = dbg_command(adr, command, len))) return err;
|
if ((err = dbg_command(adr, command, 0x8, len))) return err;
|
if ((err = dbg_go(DI_WB_GO, data, len, 1))) return err;
|
if ((err = dbg_go(DI_WB_GO, data, len, 1, 0x8))) return err;
|
if ((err = dbg_wb_status())) return err;
|
if ((err = dbg_wb_status())) return err;
|
return DBG_ERR_OK;
|
return DBG_ERR_OK;
|
}
|
}
|
|
|
/* write a block to wishbone */
|
/* write a block to wishbone */
|
int dbg_wb_write(unsigned long adr, int command, unsigned char *data, unsigned short len) {
|
int dbg_wb_write(unsigned long adr, int command, unsigned char *data, unsigned short len) {
|
int err;
|
int err;
|
if ((err = dbg_set_chain(DC_WISHBONE))) return err;
|
if ((err = dbg_set_chain(DC_WISHBONE))) return err;
|
if ((err = dbg_command(adr, command, len))) return err;
|
if ((err = dbg_command(adr, command, 0x8, len))) return err;
|
if ((err = dbg_go(DI_WB_GO, data, len, 0))) return err;
|
if ((err = dbg_go(DI_WB_GO, data, len, 0, 0x8))) return err;
|
if ((err = dbg_wb_status())) return err;
|
if ((err = dbg_wb_status())) return err;
|
return DBG_ERR_OK;
|
return DBG_ERR_OK;
|
}
|
}
|
|
|
/* read a register from cpu */
|
/* read a register from cpu */
|
int dbg_cpu_read(unsigned long adr, int command, unsigned long *data) {
|
int dbg_cpu_read(unsigned long adr, int command, unsigned long *data, int len) {
|
int err;
|
int err;
|
if ((err = dbg_set_chain(DC_CPU))) return err;
|
if ((err = dbg_set_chain(DC_CPU))) return err;
|
if ((err = dbg_command(adr, command, -1))) return err;
|
if ((err = dbg_command(adr, command, 0xa, -1))) return err;
|
if ((err = dbg_go(DI_CPU_GO, (unsigned char*)data, 4, 1))) return err;
|
if ((err = dbg_go(DI_CPU_GO, (unsigned char*)data, len, 1, 0xa))) return err;
|
return DBG_ERR_OK;
|
return DBG_ERR_OK;
|
}
|
}
|
|
|
/* write a cpu register */
|
/* write a cpu register */
|
int dbg_cpu_write(unsigned long adr, int command, unsigned long data) {
|
int dbg_cpu_write(unsigned long adr, int command, unsigned long data, int len) {
|
int err;
|
int err;
|
if ((err = dbg_set_chain(DC_CPU))) return err;
|
if ((err = dbg_set_chain(DC_CPU))) return err;
|
if ((err = dbg_command(adr, command, -1))) return err;
|
if ((err = dbg_command(adr, command, 0xa, -1))) return err;
|
if ((err = dbg_go(DI_CPU_GO, (unsigned char *)&data, 4, 0))) return err;
|
if ((err = dbg_go(DI_CPU_GO, (unsigned char *)&data, len, 0, 0xa))) return err;
|
return DBG_ERR_OK;
|
return DBG_ERR_OK;
|
}
|
}
|
|
|
/* read a word from wishbone */
|
/* read a word from wishbone */
|
int dbg_wb_read32(unsigned long adr, unsigned long *data) {
|
int dbg_wb_read32(unsigned long adr, unsigned long *data) {
|
return dbg_wb_read(adr, DI_WB_READ32, (unsigned char*)data, 4);
|
int err = dbg_wb_read(adr, DI_WB_READ32, (unsigned char*)data, 4);
|
|
*data = ntohl(*data);
|
|
return err;
|
}
|
}
|
|
|
/* write a word to wishbone */
|
/* write a word to wishbone */
|
int dbg_wb_write32(unsigned long adr, unsigned long data) {
|
int dbg_wb_write32(unsigned long adr, unsigned long data) {
|
|
data = ntohl(data);
|
return dbg_wb_write(adr, DI_WB_WRITE32, (unsigned char*)&data, 4);
|
return dbg_wb_write(adr, DI_WB_WRITE32, (unsigned char*)&data, 4);
|
}
|
}
|
|
|
/* read a block from wishbone */
|
/* read a block from wishbone */
|
int dbg_wb_read_block_32(unsigned long adr, unsigned long *data, int len) {
|
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len) {
|
return dbg_wb_read(adr, DI_WB_READ32, (unsigned char*)data, len);
|
int i, err;
|
|
//printf("%08x %08x\n", adr, len);
|
|
err = dbg_wb_read(adr, DI_WB_READ32, (unsigned char*)data, len);
|
|
for (i = 0; i < len / 4; i ++) data[i] = ntohl(data[i]);
|
|
//printf("%08x\n", err);
|
|
return err;
|
}
|
}
|
|
|
/* write a block to wishbone */
|
/* write a block to wishbone */
|
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len) {
|
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len) {
|
|
int i;
|
|
for (i = 0; i < len / 4; i ++) data[i] = ntohl(data[i]);
|
return dbg_wb_write(adr, DI_WB_WRITE32, (unsigned char*)data, len);
|
return dbg_wb_write(adr, DI_WB_WRITE32, (unsigned char*)data, len);
|
}
|
}
|
|
|
/* read a register from cpu */
|
/* read a register from cpu */
|
int dbg_cpu_read32(unsigned long adr, unsigned long *data) {
|
int dbg_cpu_read32(unsigned long adr, unsigned long *data) {
|
return dbg_cpu_read(adr, DI_CPU_READ32, data);
|
int err = dbg_cpu_read(adr, DI_CPU_READ32, data, 4);
|
|
*data = ntohl(*data);
|
|
return err;
|
}
|
}
|
|
|
/* read a register from cpu module */
|
/* read a register from cpu module */
|
int dbg_cpu_read_reg(unsigned long adr, unsigned long *data) {
|
int dbg_cpu_read_reg(unsigned long adr, unsigned char *data) {
|
return dbg_cpu_read(adr, DI_CPU_READ_REG, data);
|
return dbg_cpu_read(adr, DI_CPU_READ_REG, (unsigned long *)data, 1);
|
}
|
}
|
|
|
/* write a cpu register */
|
/* write a cpu register */
|
int dbg_cpu_write32(unsigned long adr, unsigned long data) {
|
int dbg_cpu_write32(unsigned long adr, unsigned long data) {
|
return dbg_cpu_write(adr, DI_CPU_WRITE32, data);
|
data = ntohl(data);
|
|
return dbg_cpu_write(adr, DI_CPU_WRITE32, data, 4);
|
}
|
}
|
|
|
/* write a cpu module register */
|
/* write a cpu module register */
|
int dbg_cpu_write_reg(unsigned long adr, unsigned long data) {
|
int dbg_cpu_write_reg(unsigned long adr, unsigned char data) {
|
return dbg_cpu_write(adr, DI_CPU_WRITE_REG, data);
|
unsigned long l;
|
|
*((unsigned char*)&l) = data;
|
|
return dbg_cpu_write(adr, DI_CPU_WRITE_REG, data, 1);
|
|
}
|
|
|
|
void check(char *fn, int l, int i) {
|
|
if (i != DBG_ERR_OK) {
|
|
fprintf(stderr, "%s:%d: Jtag error %d occured; exiting.\n", fn, l, i);
|
|
exit(1);
|
|
}
|
}
|
}
|
|
|
void dbg_test() {
|
void dbg_test() {
|
int i;
|
int i;
|
unsigned long npc, ppc, r1, insn, result;
|
unsigned long npc, ppc, r1, insn, result;
|
#if 0
|
unsigned char stalled;
|
#define MC_BASE_ADD 0x60000000
|
#if 1
|
#define MC_CSR_VAL 0x0f300300
|
#define MC_BASE_ADDR 0x93000000
|
#define MC_MASK_VAL 0x000000e0
|
#define FLASH_BASE_ADDR 0xf0000000
|
#define FLASH_BASE_ADD 0x04000000
|
#define FLASH_BAR_VAL FLASH_BASE_ADDR
|
#define FLASH_TMS_VAL 0x0010a10a
|
#define FLASH_AMR_VAL 0xf0000000
|
#define SDRAM_BASE_ADD 0x00000000
|
#define FLASH_WTR_VAL 0x00011009
|
#define SDRAM_TMS_VAL 0x07248230
|
#define FLASH_RTR_VAL 0x01002009
|
|
#define SDRAM_BASE_ADDR 0x00000000
|
dbg_cpu_write_reg(0, 0x01);
|
#define SDRAM_BAR_VAL SDRAM_BASE_ADDR
|
|
#define SDRAM_SIZE 0x02000000
|
dbg_wb_write32(MC_BASE_ADD + MC_CSC(0),(((FLASH_BASE_ADD & 0xffff0000) >> 5) | 0x25));
|
#define SDRAM_AMR_VAL (~(SDRAM_SIZE -1))
|
dbg_wb_write32(MC_BASE_ADD + MC_TMS(0), FLASH_TMS_VAL);
|
#define SDRAM_RATR_VAL 0x00000006
|
|
#define SDRAM_RCDR_VAL 0x00000002
|
dbg_wb_write32(MC_BASE_ADD + MC_BA_MASK, MC_MASK_VAL);
|
#define SDRAM_RCTR_VAL 0x00000006
|
dbg_wb_write32(MC_BASE_ADD + MC_CSR, MC_CSR_VAL);
|
#define SDRAM_REFCTR_VAL 0x00000006
|
|
#define SDRAM_PTR_VAL 0x00000001
|
dbg_wb_write32(MC_BASE_ADD + MC_TMS(1), SDRAM_TMS_VAL);
|
#define SDRAM_RRDR_VAL 0x00000000
|
dbg_wb_write32(MC_BASE_ADD + MC_CSC(1),(((SDRAM_BASE_ADD & 0xffff0000) >> 5) | 0x0411));
|
#define SDRAM_RIR_VAL 0x000000C0
|
|
|
|
#define MC_BAR_0 0x00
|
|
#define MC_AMR_0 0x04
|
|
#define MC_WTR_0 0x30
|
|
#define MC_RTR_0 0x34
|
|
#define MC_OSR 0xe8
|
|
#define MC_BAR_4 0x80
|
|
#define MC_AMR_4 0x84
|
|
#define MC_CCR_4 0xa0
|
|
#define MC_RATR 0xb0
|
|
#define MC_RCDR 0xc8
|
|
#define MC_RCTR 0xb4
|
|
#define MC_REFCTR 0xc4
|
|
#define MC_PTR 0xbc
|
|
#define MC_RRDR 0xb8
|
|
#define MC_RIR 0xcc
|
|
#define MC_ORR 0xe4
|
|
|
|
CHECK(dbg_cpu_write_reg(0, 0x01));
|
|
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_0, FLASH_BAR_VAL & 0xffff0000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_0, FLASH_AMR_VAL & 0xffff0000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_WTR_0, FLASH_WTR_VAL));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RTR_0, FLASH_RTR_VAL));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x40000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_4, SDRAM_BAR_VAL & 0xffff0000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_4, SDRAM_AMR_VAL & 0xffff0000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0x00ef0004));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RATR, SDRAM_RATR_VAL));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCDR, SDRAM_RCDR_VAL));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCTR, SDRAM_RCTR_VAL));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_REFCTR, SDRAM_REFCTR_VAL));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_PTR, SDRAM_PTR_VAL));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RRDR, SDRAM_RRDR_VAL));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RIR, SDRAM_RIR_VAL));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x5e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x5e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x6e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x7e000033));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x7e000033));
|
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0xc0ef0004));
|
|
|
sleep(1);
|
CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
|
|
printf("expected %x, read %x\n", 0xc0be0004, insn);
|
#endif
|
#endif
|
|
|
#if 1
|
#if 1
|
|
#define CPU_OP_ADR 0
|
|
#define CPU_SEL_ADR 1
|
#define RAM_BASE 0x00000000
|
#define RAM_BASE 0x00000000
|
/* Stall risc */
|
|
dbg_cpu_write_reg(0, 0x01);
|
|
|
|
dbg_wb_write32(RAM_BASE+0x00, 0x9c200000); /* l.addi r1,r0,0x0*/
|
/* Select cpu 0 */
|
dbg_wb_write32(RAM_BASE+0x04, 0x18400000+(RAM_BASE >> 16)); /* l.movhi r2,0x4000*/
|
CHECK(dbg_cpu_write_reg(CPU_SEL_ADR, 0x01));
|
dbg_wb_write32(RAM_BASE+0x08, 0xa8420000+((RAM_BASE + 0x30) & 0xffff));/* l.ori r2,r2,0x0*/
|
/* Stall all cpus and selected cpu 0 */
|
dbg_wb_write32(RAM_BASE+0x0c, 0x9c210001); /* l.addi r1,r1,1 */
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x05));
|
dbg_wb_write32(RAM_BASE+0x10, 0x9c210001); /* l.addi r1,r1,1 */
|
|
dbg_wb_write32(RAM_BASE+0x14, 0xd4020800); /* l.sw 0(r2),r1 */
|
/* unstall the or1200 in highland_sys */
|
dbg_wb_write32(RAM_BASE+0x18, 0x9c210001); /* l.addi r1,r1,1 */
|
CHECK(dbg_wb_write32(0xb8070000, 2));
|
dbg_wb_write32(RAM_BASE+0x1c, 0x84620000); /* l.lwz r3,0(r2) */
|
|
dbg_wb_write32(RAM_BASE+0x20, 0x03fffffb); /* l.j loop2 */
|
usleep(1000);
|
dbg_wb_write32(RAM_BASE+0x24, 0xe0211800); /* l.add r1,r1,r3 */
|
CHECK(dbg_wb_write32(RAM_BASE+0x00, 0x12345678));
|
dbg_wb_write32(RAM_BASE+0x24, 0xe0211800); /* l.add r1,r1,r3 */
|
CHECK(dbg_wb_read32(RAM_BASE+0x00, &insn));
|
|
printf("expected %x, read %x\n", 0x12345678, insn);
|
dbg_cpu_write32((0 << 11) + 17, 0x01); /* Enable exceptions */
|
if (insn != 0x12345678) exit(1);
|
dbg_cpu_write32((6 << 11) + 20, 0x2000); /* Trap causes stall */
|
|
dbg_cpu_write32((0 << 11) + 16, RAM_BASE); /* Set PC */
|
CHECK(dbg_wb_write32(RAM_BASE+0x0000, 0x11112222));
|
dbg_cpu_write32((6 << 11) + 16, 1 << 22); /* Set step bit */
|
CHECK(dbg_wb_read32(RAM_BASE+0x0000, &insn));
|
for(i = 0; i < 10; i++) dbg_cpu_write_reg(0, 0x00); /* 10x Unstall */
|
printf("expected %x, read %x\n", 0x11112222, insn);
|
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */
|
|
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */
|
CHECK(dbg_wb_write32(RAM_BASE+0x0004, 0x33334444));
|
dbg_cpu_read32(0x401, &r1); /* Read R1 */
|
CHECK(dbg_wb_write32(RAM_BASE+0x0008, 0x55556666));
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x000c, 0x77778888));
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x0010, 0x9999aaaa));
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x0014, 0xbbbbcccc));
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x0018, 0xddddeeee));
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x001c, 0xffff0000));
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x0020, 0xdeadbeaf));
|
|
|
|
CHECK(dbg_wb_read32(RAM_BASE+0x0004, &insn));
|
|
printf("expected %x, read %x\n", 0x33334444, insn);
|
|
CHECK(dbg_wb_read32(RAM_BASE+0x0000, &insn));
|
|
printf("expected %x, read %x\n", 0x11112222, insn);
|
|
CHECK(dbg_wb_read32(RAM_BASE+0x0008, &insn));
|
|
printf("expected %x, read %x\n", 0x55556666, insn);
|
|
CHECK(dbg_wb_read32(RAM_BASE+0x000c, &insn));
|
|
printf("expected %x, read %x\n", 0x77778888, insn);
|
|
CHECK(dbg_wb_read32(RAM_BASE+0x0010, &insn));
|
|
printf("expected %x, read %x\n", 0x9999aaaa, insn);
|
|
CHECK(dbg_wb_read32(RAM_BASE+0x0014, &insn));
|
|
printf("expected %x, read %x\n", 0xbbbbcccc, insn);
|
|
CHECK(dbg_wb_read32(RAM_BASE+0x0018, &insn));
|
|
printf("expected %x, read %x\n", 0xddddeeee, insn);
|
|
|
|
CHECK(dbg_wb_read32(RAM_BASE+0x001c, &insn));
|
|
printf("expected %x, read %x\n", 0xffff0000, insn);
|
|
|
|
CHECK(dbg_wb_read32(RAM_BASE+0x0020, &insn));
|
|
printf("expected %x, read %x\n", 0xdeadbeaf, insn);
|
|
|
|
if (insn != 0xdeadbeaf) exit(1);
|
|
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x00, 0xe0000005)); /* l.xor r0,r0,r0 */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x04, 0x9c200000)); /* l.addi r1,r0,0x0 */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x08, 0x18400000)); /* l.movhi r2,0x4000 */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x0c, 0xa8420030)); /* l.ori r2,r2,0x30 */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x10, 0x9c210001)); /* l.addi r1,r1,1 */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x14, 0x9c210001)); /* l.addi r1,r1,1 */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x18, 0xd4020800)); /* l.sw 0(r2),r1 */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x1c, 0x9c210001)); /* l.addi r1,r1,1 */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x20, 0x84620000)); /* l.lwz r3,0(r2) */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x24, 0x03fffffb)); /* l.j loop2 */
|
|
CHECK(dbg_wb_write32(RAM_BASE+0x28, 0xe0211800)); /* l.add r1,r1,r3 */
|
|
|
|
CHECK(dbg_cpu_write32((0 << 11) + 17, 0x01)); /* Enable exceptions */
|
|
CHECK(dbg_cpu_write32((6 << 11) + 20, 0x2000)); /* Trap causes stall */
|
|
CHECK(dbg_cpu_write32((0 << 11) + 16, RAM_BASE)); /* Set PC */
|
|
CHECK(dbg_cpu_write32((6 << 11) + 16, 1 << 22)); /* Set step bit */
|
|
for(i = 0; i < 11; i++) {
|
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x00)); /* 11x Unstall */
|
|
do CHECK(dbg_cpu_read_reg(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
|
}
|
|
|
|
CHECK(dbg_cpu_read32((0 << 11) + 16, &npc)); /* Read NPC */
|
|
CHECK(dbg_cpu_read32((0 << 11) + 18, &ppc)); /* Read PPC */
|
|
CHECK(dbg_cpu_read32(0x401, &r1)); /* Read R1 */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x4000000c, 0x40000024, 5);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 5);
|
result = npc + ppc + r1;
|
result = npc + ppc + r1;
|
|
|
dbg_cpu_write32((6 << 11) + 16, 0); /* Reset step bit */
|
CHECK(dbg_cpu_write32((6 << 11) + 16, 0)); /* Reset step bit */
|
dbg_wb_read32(RAM_BASE + 0x24, &insn); /* Set trap insn in delay slot */
|
CHECK(dbg_wb_read32(RAM_BASE + 0x28, &insn)); /* Set trap insn in delay slot */
|
dbg_wb_write32(RAM_BASE + 0x24, 0x21000001);
|
CHECK(dbg_wb_write32(RAM_BASE + 0x28, 0x21000001));
|
dbg_cpu_write_reg(0, 0x00); /* Unstall */
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x00)); /* Unstall */
|
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */
|
do CHECK(dbg_cpu_read_reg(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */
|
CHECK(dbg_cpu_read32((0 << 11) + 16, &npc)); /* Read NPC */
|
dbg_cpu_read32(0x401, &r1); /* Read R1 */
|
CHECK(dbg_cpu_read32((0 << 11) + 18, &ppc)); /* Read PPC */
|
dbg_wb_write32(RAM_BASE + 0x24, insn); /* Set back original insn */
|
CHECK(dbg_cpu_read32(0x401, &r1)); /* Read R1 */
|
|
CHECK(dbg_wb_write32(RAM_BASE + 0x28, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x4000000c, 0x40000024, 8);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 8);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
dbg_wb_read32(RAM_BASE + 0x20, &insn); /* Set trap insn in place of branch insn */
|
CHECK(dbg_wb_read32(RAM_BASE + 0x24, &insn)); /* Set trap insn in place of branch insn */
|
dbg_wb_write32(RAM_BASE + 0x20, 0x21000001);
|
CHECK(dbg_wb_write32(RAM_BASE + 0x24, 0x21000001));
|
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x0c); /* Set PC */
|
CHECK(dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x10)); /* Set PC */
|
dbg_cpu_write_reg(0, 0x00); /* Unstall */
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x00)); /* Unstall */
|
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */
|
do CHECK(dbg_cpu_read_reg(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */
|
CHECK(dbg_cpu_read32((0 << 11) + 16, &npc)); /* Read NPC */
|
dbg_cpu_read32(0x401, &r1); /* Read R1 */
|
CHECK(dbg_cpu_read32((0 << 11) + 18, &ppc)); /* Read PPC */
|
dbg_wb_write32(RAM_BASE + 0x20, insn); /* Set back original insn */
|
CHECK(dbg_cpu_read32(0x401, &r1)); /* Read R1 */
|
|
CHECK(dbg_wb_write32(RAM_BASE + 0x24, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000024, 0x40000020, 11);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000028, 0x00000024, 11);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
dbg_wb_read32(RAM_BASE + 0x1c, &insn); /* Set trap insn before branch insn */
|
CHECK(dbg_wb_read32(RAM_BASE + 0x20, &insn)); /* Set trap insn before branch insn */
|
dbg_wb_write32(RAM_BASE + 0x1c, 0x21000001);
|
CHECK(dbg_wb_write32(RAM_BASE + 0x20, 0x21000001));
|
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x20); /* Set PC */
|
CHECK(dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x24)); /* Set PC */
|
dbg_cpu_write_reg(0, 0x00); /* Unstall */
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x00)); /* Unstall */
|
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */
|
do CHECK(dbg_cpu_read_reg(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */
|
CHECK(dbg_cpu_read32((0 << 11) + 16, &npc)); /* Read NPC */
|
dbg_cpu_read32(0x401, &r1); /* Read R1 */
|
CHECK(dbg_cpu_read32((0 << 11) + 18, &ppc)); /* Read PPC */
|
dbg_wb_write32(RAM_BASE + 0x1c, insn); /* Set back original insn */
|
CHECK(dbg_cpu_read32(0x401, &r1)); /* Read R1 */
|
|
CHECK(dbg_wb_write32(RAM_BASE + 0x20, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000020, 0x4000001c, 24);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000024, 0x00000020, 24);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
|
CHECK(dbg_wb_read32(RAM_BASE + 0x1c, &insn)); /* Set trap insn behind lsu insn */
|
dbg_wb_read32(RAM_BASE + 0x18, &insn); /* Set trap insn behind lsu insn */
|
CHECK(dbg_wb_write32(RAM_BASE + 0x1c, 0x21000001));
|
dbg_wb_write32(RAM_BASE + 0x18, 0x21000001);
|
CHECK(dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x20)); /* Set PC */
|
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x1c); /* Set PC */
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x00)); /* Unstall */
|
dbg_cpu_write_reg(0, 0x00); /* Unstall */
|
do CHECK(dbg_cpu_read_reg(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */
|
CHECK(dbg_cpu_read32((0 << 11) + 16, &npc)); /* Read NPC */
|
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */
|
CHECK(dbg_cpu_read32((0 << 11) + 18, &ppc)); /* Read PPC */
|
dbg_cpu_read32(0x401, &r1); /* Read R1 */
|
CHECK(dbg_cpu_read32(0x401, &r1)); /* Read R1 */
|
dbg_wb_write32(RAM_BASE + 0x18, insn); /* Set back original insn */
|
CHECK(dbg_wb_write32(RAM_BASE + 0x1c, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x4000001c, 0x40000018, 49);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000020, 0x0000001c, 49);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
dbg_wb_read32(RAM_BASE + 0x1c, &insn); /* Set trap insn very near previous one */
|
CHECK(dbg_wb_read32(RAM_BASE + 0x20, &insn)); /* Set trap insn very near previous one */
|
dbg_wb_write32(RAM_BASE + 0x1c, 0x21000001);
|
CHECK(dbg_wb_write32(RAM_BASE + 0x20, 0x21000001));
|
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x18); /* Set PC */
|
CHECK(dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x1c)); /* Set PC */
|
dbg_cpu_write_reg(0, 0x00); /* Unstall */
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x00)); /* Unstall */
|
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */
|
do CHECK(dbg_cpu_read_reg(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */
|
CHECK(dbg_cpu_read32((0 << 11) + 16, &npc)); /* Read NPC */
|
dbg_cpu_read32(0x401, &r1); /* Read R1 */
|
CHECK(dbg_cpu_read32((0 << 11) + 18, &ppc)); /* Read PPC */
|
dbg_wb_write32(RAM_BASE + 0x1c, insn); /* Set back original insn */
|
CHECK(dbg_cpu_read32(0x401, &r1)); /* Read R1 */
|
|
CHECK(dbg_wb_write32(RAM_BASE + 0x20, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000020, 0x4000001c, 50);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000024, 0x00000020, 50);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
dbg_wb_read32(RAM_BASE + 0x0c, &insn); /* Set trap insn to the start */
|
CHECK(dbg_wb_read32(RAM_BASE + 0x10, &insn)); /* Set trap insn to the start */
|
dbg_wb_write32(RAM_BASE + 0x0c, 0x21000001);
|
CHECK(dbg_wb_write32(RAM_BASE + 0x10, 0x21000001));
|
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x1c) /* Set PC */;
|
CHECK(dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x20) /* Set PC */);
|
dbg_cpu_write_reg(0, 0x00); /* Unstall */
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x00)); /* Unstall */
|
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */
|
do CHECK(dbg_cpu_read_reg(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */
|
CHECK(dbg_cpu_read32((0 << 11) + 16, &npc)); /* Read NPC */
|
dbg_cpu_read32(0x401, &r1); /* Read R1 */
|
CHECK(dbg_cpu_read32((0 << 11) + 18, &ppc)); /* Read PPC */
|
dbg_wb_write32(RAM_BASE + 0x0c, insn); /* Set back original insn */
|
CHECK(dbg_cpu_read32(0x401, &r1)); /* Read R1 */
|
|
CHECK(dbg_wb_write32(RAM_BASE + 0x10, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000010, 0x4000000c, 99);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000014, 0x00000010, 99);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
dbg_cpu_write32((6 << 11) + 16, 1 << 22); /* Set step bit */
|
CHECK(dbg_cpu_write32((6 << 11) + 16, 1 << 22)); /* Set step bit */
|
for(i = 0; i < 5; i++) dbg_cpu_write_reg(0, 0x00); /* Unstall */
|
for(i = 0; i < 5; i++) {
|
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x00)); /* Unstall */
|
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */
|
do CHECK(dbg_cpu_read_reg(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
dbg_cpu_read32(0x401, &r1); /* Read R1 */
|
}
|
|
CHECK(dbg_cpu_read32((0 << 11) + 16, &npc)); /* Read NPC */
|
|
CHECK(dbg_cpu_read32((0 << 11) + 18, &ppc)); /* Read PPC */
|
|
CHECK(dbg_cpu_read32(0x401, &r1)); /* Read R1 */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x40000024, 0x40000020, 101);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000028, 0x00000024, 101);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x20); /* Set PC */
|
CHECK(dbg_cpu_write32((0 << 11) + 16, RAM_BASE + 0x24)); /* Set PC */
|
for(i = 0; i < 2; i++) dbg_cpu_write_reg(0, 0x00); /* Unstall */
|
for(i = 0; i < 2; i++) {
|
dbg_cpu_read32((0 << 11) + 16, &npc); /* Read NPC */
|
CHECK(dbg_cpu_write_reg(CPU_OP_ADR, 0x00)); /* Unstall */
|
dbg_cpu_read32((0 << 11) + 18, &ppc); /* Read PPC */
|
do CHECK(dbg_cpu_read_reg(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
dbg_cpu_read32(0x401, &r1); /* Read R1 */
|
}
|
|
CHECK(dbg_cpu_read32((0 << 11) + 16, &npc)); /* Read NPC */
|
|
CHECK(dbg_cpu_read32((0 << 11) + 18, &ppc)); /* Read PPC */
|
|
CHECK(dbg_cpu_read32(0x401, &r1)); /* Read R1 */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x4000000c, 0x40000024, 201);
|
printf("Expected npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 201);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
printf("result = %.8lx\n", result + 0x5eaddaa9);
|
printf("result = %.8lx\n", result ^ 0xdeaddae1);
|
#endif
|
#endif
|
}
|
}
|
|
|
int main(int argc, char *argv[]) {
|
int main(int argc, char *argv[]) {
|
char *redirstr;
|
char *redirstr;
|
