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[/] [or1k/] [trunk/] [jtag/] [jp2.c] - Diff between revs 1274 and 1277
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| Rev 1274 |
Rev 1277 |
| Line 916... |
Line 916... |
CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
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CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
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printf("expected %x, read %x\n", 0xc0bf0005, insn);
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printf("expected %x, read %x\n", 0xc0bf0005, insn);
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// SRAM initialized to 0x40000000
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// SRAM initialized to 0x40000000
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_1, SRAM_BASE & 0xffff0000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_1, SRAM_BASE & 0xffff0000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_1, SRAM_BASE & 0xffff0000)); // This is not OK
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_1, ~(SRAM_SIZE - 1) & 0xffff0000));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_1, 0xc020001f));
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CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_1, 0xc020001f));
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#endif
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#endif
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#if 1
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#if 1
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#define CPU_OP_ADR 0
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#define CPU_OP_ADR 0
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