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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [mem_if/] [flash_top.v] - Diff between revs 609 and 661

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Rev 609 Rev 661
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2002/01/23 07:50:44  lampret
 
// Added wb_err_o to flash and sram i/f for testing the buserr exception.
 
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
//
// Revision 1.1.1.1  2001/11/04 19:00:09  lampret
// Revision 1.1.1.1  2001/11/04 19:00:09  lampret
// First import.
// First import.
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integer fflash;
integer fflash;
initial fflash = $fopen("flash.log");
initial fflash = $fopen("flash.log");
always @(posedge clk)
always @(posedge clk)
        if (wb_cyc_i)
        if (wb_cyc_i)
                if (wb_stb_i & wb_we_i) begin
                if (wb_stb_i & wb_we_i) begin
                        $fdisplay(fflash, "%t Trying to write into flash at %h (%b)", $time, wb_adr_i, wb_we_i);
//                      $fdisplay(fflash, "%t Trying to write into flash at %h (%b)", $time, wb_adr_i, wb_we_i);
                        #100 $finish;
//                      #100 $finish;
 
                        if (wb_sel_i[3])
 
                                mem[{wb_adr_i[31:2], 2'b00}+0] = wb_dat_i[31:24];
 
                        if (wb_sel_i[2])
 
                                mem[{wb_adr_i[31:2], 2'b00}+1] = wb_dat_i[23:16];
 
                        if (wb_sel_i[1])
 
                                mem[{wb_adr_i[31:2], 2'b00}+2] = wb_dat_i[15:8];
 
                        if (wb_sel_i[0])
 
                                mem[{wb_adr_i[31:2], 2'b00}+3] = wb_dat_i[7:0];
 
                        $fdisplay(fflash, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);
                end else if (wb_ack_o)
                end else if (wb_ack_o)
                        $fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
                        $fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
// synopsys translate_on
// synopsys translate_on
 
 
endmodule
endmodule

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