OpenCores

Rev 39	Rev 56
Line 15...	Line 15...
`*/`	`*/`
`#include "asm.h"`	`#include "asm.h"`

`.data`	`.data`
`.align 8`	`.align 8`
`SYM(environ): ! this is the first address in the data section`	`.ascii "DaTa" ! this is the first address in the data section`
	`.long SYM(sdata)`
	`SYM(environ):`
`.long 0`	`.long 0`

`.text`	`.text`
`.align 8`	`.align 8`

`SYM(win_ovf_trap):`
`sethi %hi(win_ovf), %l3`
`jmpl %lo(win_ovf)+%l3, %g0`
`mov %wim, %l0`
`nop`

`SYM(win_unf_trap):`
`sethi %hi(win_unf), %l3`
`jmpl %lo(win_unf)+%l3, %g0`
`mov %wim, %l0`
`nop`

`SYM(no_fpu_trap): ! Come here when no fpu exists.`
`jmpl %l2, %g0 ! This just skips the`
`rett %l2+4 ! offending instruction.`

`.globl SYM(_start)`	`.globl SYM(_start)`
`SYM(_start):`	`SYM(_start):`
`.globl SYM(start)`	`.globl SYM(start)`
`SYM(start):`	`SYM(start):`
`/* see if the stack is already setup. if not, then default`	`/* see if the stack is already setup. if not, then default`
Line 110...	Line 96...
`bset %l1, %l0`	`bset %l1, %l0`
`! mov %l0, %psr`	`! mov %l0, %psr`

`std %l4, [2 * 16] ! Restore original trap routine`	`std %l4, [2 * 16] ! Restore original trap routine`


`/*`	`/*`
`* Move the data segment from it's ROM address to RAM where it`	`* Move the data segment from it's ROM address to RAM where it`
`* belongs.`	`* belongs.`
`*/`	`*/`

`relocd:`	`relocd:`
	`#if 0 /* This code is broken. FIXME */`
`set (_sdata),%g2 ! %g2 = start of data in aout file`	`set (_sdata),%g2 ! %g2 = start of data in aout file`
`set SYM(environ),%g4 ! %g4 = actual data base address`	`set SYM(environ),%g4 ! %g4 = actual data base address`
`set (_edata),%g3 ! %g3 = end of where data should go`	`set (_edata),%g3 ! %g3 = end of where data should go`
`subcc %g3, %g4, %g5 ! %g5 = length of data`	`subcc %g3, %g4, %g5 ! %g5 = length of data`

Line 129...	Line 118...
`be init`	`be init`
`mvdata:`	`mvdata:`
`subcc %g5, 8, %g5`	`subcc %g5, 8, %g5`
`ldd [%g2 + %g5], %g6`	`ldd [%g2 + %g5], %g6`
`bg mvdata`	`bg mvdata`
	`#endif`

`/*`	`/*`
`* initialize target specific stuff. Only execute these`	`* initialize target specific stuff. Only execute these`
`* functions it they exist.`	`* functions it they exist.`
`*/`	`*/`
Line 170...	Line 160...
`*/`	`*/`
`.globl SYM(_exit)`	`.globl SYM(_exit)`
`SYM(_exit):`	`SYM(_exit):`
`call 0`	`call 0`
`nop`	`nop`

	`/*`
	`* Trap handlers.`
	`*/`

	`.align 8`

	`SYM(win_ovf_trap):`
	`sethi %hi(SYM(win_ovf)), %l3`
	`jmpl %lo(SYM(win_ovf))+%l3, %g0`
	`mov %wim, %l0`
	`nop`

	`SYM(win_unf_trap):`
	`sethi %hi(SYM(win_unf)), %l3`
	`jmpl %lo(SYM(win_unf))+%l3, %g0`
	`mov %wim, %l0`
	`nop`

	`SYM(no_fpu_trap): ! Come here when no fpu exists.`
	`jmpl %l2, %g0 ! This just skips the`
	`rett %l2+4 ! offending instruction.`

Line 15...

*/

*/

#include "asm.h"

#include "asm.h"

.data

.data

        .align  8

        .align  8

SYM(environ):                   ! this is the first address in the data section

        .ascii  "DaTa"          ! this is the first address in the data section

        .long   SYM(sdata)

SYM(environ):

        .long   0

        .long   0

        .text

        .text

        .align 8

        .align 8

SYM(win_ovf_trap):

        sethi %hi(win_ovf), %l3

        jmpl %lo(win_ovf)+%l3, %g0

        mov %wim, %l0

nop

SYM(win_unf_trap):

        sethi %hi(win_unf), %l3

        jmpl %lo(win_unf)+%l3, %g0

        mov %wim, %l0

nop

SYM(no_fpu_trap):                       ! Come here when no fpu exists.

        jmpl %l2, %g0                   ! This just skips the

        rett %l2+4                      ! offending instruction.

        .globl SYM(_start)

        .globl SYM(_start)

SYM(_start):

SYM(_start):

        .globl SYM(start)

        .globl SYM(start)

SYM(start):

SYM(start):

        /* see if the stack is already setup. if not, then default

        /* see if the stack is already setup. if not, then default

Line 110...

Line 96...

        bset %l1, %l0

        bset %l1, %l0

!       mov %l0, %psr

!       mov %l0, %psr

        std %l4, [2 * 16]                       ! Restore original trap routine

        std %l4, [2 * 16]                       ! Restore original trap routine

/*

/*

 * Move the data segment from it's ROM address to RAM where it

 * Move the data segment from it's ROM address to RAM where it

 * belongs.

 * belongs.

*/

*/

relocd:

relocd:

#if 0   /* This code is broken.  FIXME */

        set (_sdata),%g2                                ! %g2 = start of data in aout file

        set (_sdata),%g2                                ! %g2 = start of data in aout file

        set SYM(environ),%g4                    ! %g4 = actual data base address

        set SYM(environ),%g4                    ! %g4 = actual data base address

        set (_edata),%g3                                ! %g3 = end of where data should go

        set (_edata),%g3                                ! %g3 = end of where data should go

        subcc   %g3, %g4, %g5                   ! %g5 = length of data

        subcc   %g3, %g4, %g5                   ! %g5 = length of data

Line 129...

Line 118...

        be      init

        be      init

mvdata:

mvdata:

        subcc   %g5, 8, %g5

        subcc   %g5, 8, %g5

        ldd     [%g2 + %g5], %g6

        ldd     [%g2 + %g5], %g6

        bg      mvdata

        bg      mvdata

#endif

/*

/*

 * initialize target specific stuff. Only execute these

 * initialize target specific stuff. Only execute these

 * functions it they exist.

 * functions it they exist.

*/

*/

Line 170...

Line 160...

*/

*/

        .globl  SYM(_exit)

        .globl  SYM(_exit)

SYM(_exit):

SYM(_exit):

        call    0

        call    0

nop

nop

/*

 * Trap handlers.

*/

        .align 8

SYM(win_ovf_trap):

        sethi %hi(SYM(win_ovf)), %l3

        jmpl %lo(SYM(win_ovf))+%l3, %g0

        mov %wim, %l0

nop

SYM(win_unf_trap):

        sethi %hi(SYM(win_unf)), %l3

        jmpl %lo(SYM(win_unf))+%l3, %g0

        mov %wim, %l0

nop

SYM(no_fpu_trap):                       ! Come here when no fpu exists.

        jmpl %l2, %g0                   ! This just skips the

        rett %l2+4                      ! offending instruction.

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