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[/] [or1k/] [trunk/] [newlib/] [libgloss/] [sparc/] [sparclite.h] - Diff between revs 39 and 56

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Rev 39 Rev 56
Line 23... Line 23...
    __asm__ volatile ("lda [%r1]%2,%0" : "=r" (val) : "rJ" (LOC), "I" (ASI)); \
    __asm__ volatile ("lda [%r1]%2,%0" : "=r" (val) : "rJ" (LOC), "I" (ASI)); \
    val;                                                                \
    val;                                                                \
  })
  })
 
 
#define write_asi(ASI, LOC, VAL) \
#define write_asi(ASI, LOC, VAL) \
  __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI));
  __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI))
 
 
/* Use this when modifying registers that cause memory to be modified.  This
/* Use this when modifying registers that cause memory to be modified.  This
   will cause GCC to reload all values after this point.  */
   will cause GCC to reload all values after this point.  */
 
 
#define write_asi_volatile(ASI, LOC, VAL) \
#define write_asi_volatile(ASI, LOC, VAL) \
  __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI) \
  __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI) \
                    : "memory");
                    : "memory")
 
 
/* Read the PSR (processor state register). */
/* Read the PSR (processor state register). */
 
 
#define read_psr()                                                      \
#define read_psr()                                                      \
  ({                                                                    \
  ({                                                                    \
Line 44... Line 44...
  })
  })
 
 
/* Write the PSR. */
/* Write the PSR. */
 
 
#define write_psr(VAL)                                                  \
#define write_psr(VAL)                                                  \
  __asm__ ("mov %0, %%psr \n nop \n nop \n nop" : : "r" (VAL));
  __asm__ ("mov %0, %%psr \n nop \n nop \n nop" : : "r" (VAL))
 
 
 
/* Read the specified Ancillary State Register. */
 
 
 
#define read_asr(REG) read_asr1(REG)
 
#define read_asr1(REG)                                                  \
 
  ({                                                                    \
 
    unsigned int val;                                                   \
 
    __asm__ ("rd %%asr" #REG ",%0" : "=r" (val));                       \
 
    val;                                                                \
 
  })
 
 
 
/* Write the specified Ancillary State Register. */
 
 
 
#define write_asr(REG, VAL) write_asr1(REG, VAL)
 
#define write_asr1(REG, VAL)                                            \
 
    __asm__ ("wr %0, 0, %%asr" #REG : : "r" (VAL))
 
 
/* Set window size for window overflow and underflow trap handlers.  Better to
/* Set window size for window overflow and underflow trap handlers.  Better to
   do this at at compile time than to calculate them at compile time each time
   do this at at compile time than to calculate them at compile time each time
   we get a window overflow/underflow trap.  */
   we get a window overflow/underflow trap.  */
 
 

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