OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Diff between revs 589 and 595

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 589 Rev 595
Line 43... Line 43...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2002/01/18 07:56:00  lampret
 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
 
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
Line 292... Line 295...
wire    [31:0]                  spr_dat_npc;
wire    [31:0]                  spr_dat_npc;
wire    [31:0]                   spr_dat_ppc;
wire    [31:0]                   spr_dat_ppc;
wire    [31:0]                   spr_dat_mac;
wire    [31:0]                   spr_dat_mac;
wire                            force_dslot_fetch;
wire                            force_dslot_fetch;
wire                            has_dslot;
wire                            has_dslot;
 
wire                            ex_void;
wire                            if_stall;
wire                            if_stall;
wire                            id_macrc_op;
wire                            id_macrc_op;
wire                            ex_macrc_op;
wire                            ex_macrc_op;
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire    [31:0]                   mult_mac_result;
wire    [31:0]                   mult_mac_result;
Line 443... Line 447...
        .wbforw_valid(wbforw_valid),
        .wbforw_valid(wbforw_valid),
        .sig_syscall(sig_syscall),
        .sig_syscall(sig_syscall),
        .sig_trap(sig_trap),
        .sig_trap(sig_trap),
        .force_dslot_fetch(force_dslot_fetch),
        .force_dslot_fetch(force_dslot_fetch),
        .has_dslot(has_dslot),
        .has_dslot(has_dslot),
 
        .ex_void(ex_void),
        .id_macrc_op(id_macrc_op),
        .id_macrc_op(id_macrc_op),
        .ex_macrc_op(ex_macrc_op),
        .ex_macrc_op(ex_macrc_op),
        .rfe(rfe),
        .rfe(rfe),
        .except_illegal(except_illegal)
        .except_illegal(except_illegal)
);
);
Line 688... Line 693...
        .extend_flush(extend_flush),
        .extend_flush(extend_flush),
        .except_type(except_type),
        .except_type(except_type),
        .except_start(except_start),
        .except_start(except_start),
        .except_started(except_started),
        .except_started(except_started),
        .except_stop(except_stop),
        .except_stop(except_stop),
        .has_dslot(has_dslot),
        .ex_void(ex_void),
        .spr_dat_ppc(spr_dat_ppc),
        .spr_dat_ppc(spr_dat_ppc),
        .spr_dat_npc(spr_dat_npc),
        .spr_dat_npc(spr_dat_npc),
 
 
        .datain(operand_b),
        .datain(operand_b),
        .du_dsr(du_dsr),
        .du_dsr(du_dsr),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.