| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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| Line 187... |
Line 190... |
hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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`OR1200_DCFSM_DOLOAD:
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`OR1200_DCFSM_DOLOAD:
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if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)
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if (!dc_en)
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // load aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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else if (biudata_error) begin // load terminated with an error
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else if (biudata_error) begin // load terminated with an error
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| Line 216... |
Line 221... |
load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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else // load in-progress
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else // load in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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`OR1200_DCFSM_LREFILL3 : begin
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`OR1200_DCFSM_LREFILL3 : begin
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if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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if (!dc_en)
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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cnt <= #1 cnt - 'd1;
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cnt <= #1 cnt - 'd1;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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end
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end
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else if (biudata_valid) begin // last load of line refill
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else if (biudata_valid) begin // last load of line refill
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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load <= #1 1'b0;
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load <= #1 1'b0;
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end
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end
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end
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end
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`OR1200_DCFSM_DOSTORE:
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`OR1200_DCFSM_DOSTORE:
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if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)
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if (!dc_en)
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (hitmiss_eval & !(dcdmmu_cyc_i & dcdmmu_stb_i)) begin // store aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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end
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end
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else if (biudata_error) begin // store terminated with an error
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else if (biudata_error) begin // store terminated with an error
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| Line 256... |
Line 265... |
store <= #1 1'b0;
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store <= #1 1'b0;
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end
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end
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else // store write-through in-progress
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else // store write-through in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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`OR1200_DCFSM_SREFILL4 : begin
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`OR1200_DCFSM_SREFILL4 : begin
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if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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if (!dc_en)
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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cnt <= #1 cnt - 'd1;
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cnt <= #1 cnt - 'd1;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
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end
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end
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else if (biudata_valid) begin // last load of line refill
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else if (biudata_valid) begin // last load of line refill
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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