Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.41 2004/05/09 20:03:20 lampret
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// By default l.cust5 insns are disabled
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//
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// Revision 1.40 2004/05/09 19:49:04 lampret
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// Revision 1.40 2004/05/09 19:49:04 lampret
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// Added some l.cust5 custom instructions as example
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// Added some l.cust5 custom instructions as example
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//
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//
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// Revision 1.39 2004/04/08 11:00:46 simont
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// Revision 1.39 2004/04/08 11:00:46 simont
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// Add support for 512B instruction cache.
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// Add support for 512B instruction cache.
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Line 307... |
Line 310... |
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//
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//
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// Target FPGA memories
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// Target FPGA memories
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//
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//
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//`define OR1200_ALTERA_LPM
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//`define OR1200_ALTERA_LPM
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`define OR1200_XILINX_RAMB4
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//`define OR1200_XILINX_RAMB4
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//`define OR1200_XILINX_RAM32X1D
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//`define OR1200_XILINX_RAM32X1D
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//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
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//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
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|
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//
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//
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// Do not implement Data cache
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// Do not implement Data cache
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//
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//
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//`define OR1200_NO_DC
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`define OR1200_NO_DC
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|
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//
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//
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// Do not implement Insn cache
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// Do not implement Insn cache
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//
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//
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//`define OR1200_NO_IC
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`define OR1200_NO_IC
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|
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//
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//
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// Do not implement Data MMU
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// Do not implement Data MMU
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//
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//
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//`define OR1200_NO_DMMU
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`define OR1200_NO_DMMU
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|
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//
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//
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// Do not implement Insn MMU
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// Do not implement Insn MMU
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//
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//
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//`define OR1200_NO_IMMU
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`define OR1200_NO_IMMU
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|
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//
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//
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// Select between ASIC and generic multiplier
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// Select between ASIC and generic multiplier
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//
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//
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// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
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// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
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Line 566... |
Line 569... |
//
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//
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// Memory macro w/ two ports (see or1200_tpram_32x32.v)
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// Memory macro w/ two ports (see or1200_tpram_32x32.v)
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// `define OR1200_RFRAM_TWOPORT
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// `define OR1200_RFRAM_TWOPORT
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//
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//
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// Memory macro dual port (see or1200_dpram_32x32.v)
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// Memory macro dual port (see or1200_dpram_32x32.v)
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`define OR1200_RFRAM_DUALPORT
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//`define OR1200_RFRAM_DUALPORT
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//
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//
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// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
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// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
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//`define OR1200_RFRAM_GENERIC
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`define OR1200_RFRAM_GENERIC
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|
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//
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//
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// Type of mem2reg aligner to implement.
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// Type of mem2reg aligner to implement.
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//
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//
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// Once OR1200_IMPL_MEM2REG2 yielded faster
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// Once OR1200_IMPL_MEM2REG2 yielded faster
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Line 964... |
Line 967... |
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// Define if you want trace buffer
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// Define if you want trace buffer
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// (for now only available for Xilinx Virtex FPGAs)
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// (for now only available for Xilinx Virtex FPGAs)
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`ifdef OR1200_ASIC
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`ifdef OR1200_ASIC
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`else
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`else
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`define OR1200_DU_TB_IMPLEMENTED
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//`define OR1200_DU_TB_IMPLEMENTED
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`endif
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`endif
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|
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//
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//
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// Address offsets of DU registers inside DU group
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// Address offsets of DU registers inside DU group
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//
|
//
|
// To not implement a register, do not define its address
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// To not implement a register, doq not define its address
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//
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//
|
`ifdef OR1200_DU_HWBKPTS
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`ifdef OR1200_DU_HWBKPTS
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`define OR1200_DU_DVR0 11'd0
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`define OR1200_DU_DVR0 11'd0
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`define OR1200_DU_DVR1 11'd1
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`define OR1200_DU_DVR1 11'd1
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`define OR1200_DU_DVR2 11'd2
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`define OR1200_DU_DVR2 11'd2
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