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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 1288 and 1293

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.41  2004/05/09 20:03:20  lampret
 
// By default l.cust5 insns are disabled
 
//
// Revision 1.40  2004/05/09 19:49:04  lampret
// Revision 1.40  2004/05/09 19:49:04  lampret
// Added some l.cust5 custom instructions as example
// Added some l.cust5 custom instructions as example
//
//
// Revision 1.39  2004/04/08 11:00:46  simont
// Revision 1.39  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
// Add support for 512B instruction cache.
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//
//
// Target FPGA memories
// Target FPGA memories
//
//
//`define OR1200_ALTERA_LPM
//`define OR1200_ALTERA_LPM
`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
 
 
//
//
// Do not implement Data cache
// Do not implement Data cache
//
//
//`define OR1200_NO_DC
`define OR1200_NO_DC
 
 
//
//
// Do not implement Insn cache
// Do not implement Insn cache
//
//
//`define OR1200_NO_IC
`define OR1200_NO_IC
 
 
//
//
// Do not implement Data MMU
// Do not implement Data MMU
//
//
//`define OR1200_NO_DMMU
`define OR1200_NO_DMMU
 
 
//
//
// Do not implement Insn MMU
// Do not implement Insn MMU
//
//
//`define OR1200_NO_IMMU
`define OR1200_NO_IMMU
 
 
//
//
// Select between ASIC and generic multiplier
// Select between ASIC and generic multiplier
//
//
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
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//
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
// `define OR1200_RFRAM_TWOPORT
// `define OR1200_RFRAM_TWOPORT
//
//
// Memory macro dual port (see or1200_dpram_32x32.v)
// Memory macro dual port (see or1200_dpram_32x32.v)
`define OR1200_RFRAM_DUALPORT
//`define OR1200_RFRAM_DUALPORT
//
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
//`define OR1200_RFRAM_GENERIC
`define OR1200_RFRAM_GENERIC
 
 
//
//
// Type of mem2reg aligner to implement.
// Type of mem2reg aligner to implement.
//
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// Once OR1200_IMPL_MEM2REG2 yielded faster
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// Define if you want trace buffer
// Define if you want trace buffer
// (for now only available for Xilinx Virtex FPGAs)
// (for now only available for Xilinx Virtex FPGAs)
`ifdef OR1200_ASIC
`ifdef OR1200_ASIC
`else
`else
`define OR1200_DU_TB_IMPLEMENTED
//`define OR1200_DU_TB_IMPLEMENTED
`endif
`endif
 
 
//
//
// Address offsets of DU registers inside DU group
// Address offsets of DU registers inside DU group
//
//
// To not implement a register, do not define its address
// To not implement a register, doq not define its address
//
//
`ifdef OR1200_DU_HWBKPTS
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DVR0          11'd0
`define OR1200_DU_DVR0          11'd0
`define OR1200_DU_DVR1          11'd1
`define OR1200_DU_DVR1          11'd1
`define OR1200_DU_DVR2          11'd2
`define OR1200_DU_DVR2          11'd2

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