| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/10/17 20:04:40 lampret
|
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
|
//
|
// Revision 1.3 2002/02/11 04:33:17 lampret
|
// Revision 1.3 2002/02/11 04:33:17 lampret
|
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
|
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
|
//
|
//
|
// Revision 1.2 2002/01/28 01:16:00 lampret
|
// Revision 1.2 2002/01/28 01:16:00 lampret
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
| Line 80... |
Line 83... |
// I/F for translation
|
// I/F for translation
|
tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
|
tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
|
|
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
|
mbist_si_i, mbist_so_o, mbist_ctrl_i,
|
`endif
|
`endif
|
|
|
// SPR access
|
// SPR access
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
|
);
|
);
|
| Line 117... |
Line 120... |
|
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
//
|
//
|
// RAM BIST
|
// RAM BIST
|
//
|
//
|
input scanb_rst,
|
input mbist_si_i;
|
scanb_si,
|
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
|
scanb_en,
|
output mbist_so_o;
|
scanb_clk;
|
|
output scanb_so;
|
|
`endif
|
`endif
|
|
|
//
|
//
|
// SPR access
|
// SPR access
|
//
|
//
|
| Line 151... |
Line 152... |
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
|
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
//
|
//
|
// RAM BIST
|
// RAM BIST
|
//
|
//
|
wire scanb_mr_so;
|
wire mbist_mr_so;
|
wire scanb_tr_so;
|
wire mbist_tr_so;
|
wire scanb_mr_si = scanb_si;
|
wire mbist_mr_si = mbist_si_i;
|
wire scanb_tr_si = scanb_mr_so;
|
wire mbist_tr_si = mbist_mr_so;
|
assign scanb_so = scanb_tr_so;
|
assign mbist_so_o = mbist_tr_so;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Implemented bits inside match and translate registers
|
// Implemented bits inside match and translate registers
|
//
|
//
|
| Line 244... |
Line 245... |
or1200_spram_64x14 dtlb_mr_ram(
|
or1200_spram_64x14 dtlb_mr_ram(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.scanb_rst(scanb_rst),
|
.mbist_si_i(mbist_mr_si),
|
.scanb_si(scanb_mr_si),
|
.mbist_so_o(mbist_mr_so),
|
.scanb_so(scanb_mr_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.scanb_en(scanb_en),
|
|
.scanb_clk(scanb_clk),
|
|
`endif
|
`endif
|
.ce(tlb_mr_en),
|
.ce(tlb_mr_en),
|
.we(tlb_mr_we),
|
.we(tlb_mr_we),
|
.oe(1'b1),
|
.oe(1'b1),
|
.addr(tlb_index),
|
.addr(tlb_index),
|
| Line 266... |
Line 265... |
or1200_spram_64x24 dtlb_tr_ram(
|
or1200_spram_64x24 dtlb_tr_ram(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.scanb_rst(scanb_rst),
|
.mbist_si_i(mbist_tr_si),
|
.scanb_si(scanb_tr_si),
|
.mbist_so_o(mbist_tr_so),
|
.scanb_so(scanb_tr_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.scanb_en(scanb_en),
|
|
.scanb_clk(scanb_clk),
|
|
`endif
|
`endif
|
.ce(tlb_tr_en),
|
.ce(tlb_tr_en),
|
.we(tlb_tr_we),
|
.we(tlb_tr_we),
|
.oe(1'b1),
|
.oe(1'b1),
|
.addr(tlb_index),
|
.addr(tlb_index),
|
