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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dmmu_tlb.v] - Diff between revs 1267 and 1293
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| Rev 1267 |
Rev 1293 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.4.4.1 2003/12/09 11:46:48 simons
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// Revision 1.4.4.1 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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//
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// Revision 1.4 2002/10/17 20:04:40 lampret
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// Revision 1.4 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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| Line 257... |
Line 260... |
.ce(tlb_mr_en),
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.ce(tlb_mr_en),
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.we(tlb_mr_we),
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.we(tlb_mr_we),
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.oe(1'b1),
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.oe(1'b1),
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.addr(tlb_index),
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.addr(tlb_index),
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.di(tlb_mr_ram_in),
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.di(tlb_mr_ram_in),
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.do(tlb_mr_ram_out)
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.doq(tlb_mr_ram_out)
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);
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);
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//
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//
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// Instantiation of DTLB Translate Registers
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// Instantiation of DTLB Translate Registers
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//
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//
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| Line 277... |
Line 280... |
.ce(tlb_tr_en),
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.ce(tlb_tr_en),
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.we(tlb_tr_we),
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.we(tlb_tr_we),
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.oe(1'b1),
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.oe(1'b1),
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.addr(tlb_index),
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.addr(tlb_index),
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.di(tlb_tr_ram_in),
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.di(tlb_tr_ram_in),
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.do(tlb_tr_ram_out)
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.doq(tlb_tr_ram_out)
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);
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);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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