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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 504 and 573

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Rev 504	Rev 573
Line 59...	Line 59...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/01/03 08:16:15 lampret`
	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
	`//`
`// Revision 1.10 2001/11/05 14:48:00 lampret`	`// Revision 1.10 2001/11/05 14:48:00 lampret`
`// Added missing endif`	`// Added missing endif`
`//`	`//`
`// Revision 1.9 2001/11/02 18:57:14 lampret`	`// Revision 1.9 2001/11/02 18:57:14 lampret`
`// Modified virtual silicon instantiations.`	`// Modified virtual silicon instantiations.`
Line 237...	Line 240...
`//`	`//`

`//`	`//`
`// Block 0`	`// Block 0`
`//`	`//`
`xcv_ram32x8d xcv_ram32x8d_0 (`	`or1200_xcv_ram32x8d xcv_ram32x8d_0 (`
`.DPO(do_a[7:0]),`	`.DPO(do_a[7:0]),`
`.SPO(),`	`.SPO(),`
`.A(addr_b),`	`.A(addr_b),`
`.D(di_b[7:0]),`	`.D(di_b[7:0]),`
`.DPRA(addr_a),`	`.DPRA(addr_a),`
Line 250...	Line 253...
`);`	`);`

`//`	`//`
`// Block 1`	`// Block 1`
`//`	`//`
`xcv_ram32x8d xcv_ram32x8d_1 (`	`or1200_xcv_ram32x8d xcv_ram32x8d_1 (`
`.DPO(do_a[15:8]),`	`.DPO(do_a[15:8]),`
`.SPO(),`	`.SPO(),`
`.A(addr_b),`	`.A(addr_b),`
`.D(di_b[15:8]),`	`.D(di_b[15:8]),`
`.DPRA(addr_a),`	`.DPRA(addr_a),`
Line 264...	Line 267...


`//`	`//`
`// Block 2`	`// Block 2`
`//`	`//`
`xcv_ram32x8d xcv_ram32x8d_2 (`	`or1200_xcv_ram32x8d xcv_ram32x8d_2 (`
`.DPO(do_a[23:16]),`	`.DPO(do_a[23:16]),`
`.SPO(),`	`.SPO(),`
`.A(addr_b),`	`.A(addr_b),`
`.D(di_b[23:16]),`	`.D(di_b[23:16]),`
`.DPRA(addr_a),`	`.DPRA(addr_a),`
Line 277...	Line 280...
`);`	`);`

`//`	`//`
`// Block 3`	`// Block 3`
`//`	`//`
`xcv_ram32x8d xcv_ram32x8d_3 (`	`or1200_xcv_ram32x8d xcv_ram32x8d_3 (`
`.DPO(do_a[31:24]),`	`.DPO(do_a[31:24]),`
`.SPO(),`	`.SPO(),`
`.A(addr_b),`	`.A(addr_b),`
`.D(di_b[31:24]),`	`.D(di_b[31:24]),`
`.DPRA(addr_a),`	`.DPRA(addr_a),`

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 504 and 573