URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 597 and 610

Rev 597	Rev 610
Line 59...	Line 59...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2002/01/19 14:10:22 lampret`
	`// Fixed OR1200_XILINX_RAM32X1D.`
	`//`
`// Revision 1.2 2002/01/15 06:12:22 lampret`	`// Revision 1.2 2002/01/15 06:12:22 lampret`
`// Fixed module name when compiling with OR1200_XILINX_RAM32X1D`	`// Fixed module name when compiling with OR1200_XILINX_RAM32X1D`
`//`	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
Line 243...	Line 246...
`//`	`//`

`reg [4:0] addr_a_r;`	`reg [4:0] addr_a_r;`

`always @(posedge clk_a or posedge rst_a)`	`always @(posedge clk_a or posedge rst_a)`
`if (ce_a)`	`if (rst_a)`
	`addr_a_r <= #1 5'b00000;`
	`else if (ce_a)`
`addr_a_r <= #1 addr_a;`	`addr_a_r <= #1 addr_a;`

`//`	`//`
`// Block 0`	`// Block 0`
`//`	`//`