| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2005/01/07 09:35:08 andreje
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// du_hwbkpt disabled when debug unit not implemented
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//
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// Revision 1.10 2004/04/05 08:29:57 lampret
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// Revision 1.10 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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//
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//
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// Revision 1.9.4.4 2004/02/11 01:40:11 lampret
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// Revision 1.9.4.4 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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| Line 1695... |
Line 1698... |
tb_timstmp <= #1 tb_timstmp + 32'd1;
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tb_timstmp <= #1 tb_timstmp + 32'd1;
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//
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//
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// Trace buffer RAMs
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// Trace buffer RAMs
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//
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//
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RAMB4_S16_S16 tbia_ramb4_s16_0(
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.CLKA(clk),
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.RSTA(rst),
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.ADDRA(tb_wadr),
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.DIA(spr_dat_npc[15:0]),
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.ENA(1'b1),
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.WEA(tb_enw),
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.DOA(),
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.CLKB(clk),
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.RSTB(rst),
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.ADDRB(spr_addr[7:0]),
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.DIB(16'h0000),
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.ENB(1'b1),
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.WEB(1'b0),
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.DOB(tbia_dat_o[15:0])
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);
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RAMB4_S16_S16 tbia_ramb4_s16_1(
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.CLKA(clk),
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.RSTA(rst),
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.ADDRA(tb_wadr),
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.DIA(spr_dat_npc[31:16]),
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.ENA(1'b1),
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.WEA(tb_enw),
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.DOA(),
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.CLKB(clk),
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.RSTB(rst),
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.ADDRB(spr_addr[7:0]),
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.DIB(16'h0000),
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.ENB(1'b1),
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.WEB(1'b0),
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.DOB(tbia_dat_o[31:16])
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);
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RAMB4_S16_S16 tbim_ramb4_s16_0(
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or1200_dpram_256x32 tbia_ram(
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.CLKA(clk),
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.clk_a(clk),
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.RSTA(rst),
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.rst_a(rst),
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.ADDRA(tb_wadr),
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.addr_a(spr_addr[7:0]),
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.DIA(ex_insn[15:0]),
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.ce_a(1'b1),
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.ENA(1'b1),
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.oe_a(1'b1),
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.WEA(tb_enw),
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.do_a(tbia_dat_o),
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.DOA(),
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.clk_b(clk),
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.CLKB(clk),
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.rst_b(rst),
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.RSTB(rst),
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.addr_b(tb_wadr),
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.ADDRB(spr_addr[7:0]),
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.di_b(spr_dat_npc),
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.DIB(16'h0000),
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.ce_b(1'b1),
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.ENB(1'b1),
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.we_b(tb_enw)
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.WEB(1'b0),
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.DOB(tbim_dat_o[15:0])
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);
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RAMB4_S16_S16 tbim_ramb4_s16_1(
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.CLKA(clk),
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.RSTA(rst),
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.ADDRA(tb_wadr),
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.DIA(ex_insn[31:16]),
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.ENA(1'b1),
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.WEA(tb_enw),
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.DOA(),
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.CLKB(clk),
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.RSTB(rst),
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.ADDRB(spr_addr[7:0]),
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.DIB(16'h0000),
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.ENB(1'b1),
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.WEB(1'b0),
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.DOB(tbim_dat_o[31:16])
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);
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RAMB4_S16_S16 tbar_ramb4_s16_0(
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.CLKA(clk),
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.RSTA(rst),
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.ADDRA(tb_wadr),
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.DIA(rf_dataw[15:0]),
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.ENA(1'b1),
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.WEA(tb_enw),
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.DOA(),
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.CLKB(clk),
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.RSTB(rst),
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.ADDRB(spr_addr[7:0]),
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.DIB(16'h0000),
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.ENB(1'b1),
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.WEB(1'b0),
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.DOB(tbar_dat_o[15:0])
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);
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);
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RAMB4_S16_S16 tbar_ramb4_s16_1(
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or1200_dpram_256x32 tbim_ram(
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.CLKA(clk),
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.clk_a(clk),
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.RSTA(rst),
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.rst_a(rst),
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.ADDRA(tb_wadr),
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.addr_a(spr_addr[7:0]),
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.DIA(rf_dataw[31:16]),
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.ce_a(1'b1),
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.ENA(1'b1),
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.oe_a(1'b1),
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.WEA(tb_enw),
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.do_a(tbim_dat_o),
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.DOA(),
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.clk_b(clk),
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.CLKB(clk),
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.rst_b(rst),
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.RSTB(rst),
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.addr_b(tb_wadr),
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.ADDRB(spr_addr[7:0]),
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.di_b(ex_insn),
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.DIB(16'h0000),
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.ce_b(1'b1),
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.ENB(1'b1),
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.we_b(tb_enw)
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.WEB(1'b0),
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.DOB(tbar_dat_o[31:16])
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);
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);
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RAMB4_S16_S16 tbts_ramb4_s16_0(
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or1200_dpram_256x32 tbar_ram(
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.CLKA(clk),
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.clk_a(clk),
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.RSTA(rst),
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.rst_a(rst),
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.ADDRA(tb_wadr),
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.addr_a(spr_addr[7:0]),
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.DIA(tb_timstmp[15:0]),
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.ce_a(1'b1),
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.ENA(1'b1),
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.oe_a(1'b1),
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.WEA(tb_enw),
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.do_a(tbar_dat_o),
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.DOA(),
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.clk_b(clk),
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.CLKB(clk),
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.rst_b(rst),
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.RSTB(rst),
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.addr_b(tb_wadr),
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.ADDRB(spr_addr[7:0]),
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.di_b(rf_dataw),
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.DIB(16'h0000),
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.ce_b(1'b1),
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.ENB(1'b1),
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.we_b(tb_enw)
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.WEB(1'b0),
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.DOB(tbts_dat_o[15:0])
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);
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);
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RAMB4_S16_S16 tbts_ramb4_s16_1(
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or1200_dpram_256x32 tbts_ram(
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.CLKA(clk),
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.clk_a(clk),
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.RSTA(rst),
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.rst_a(rst),
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.ADDRA(tb_wadr),
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.addr_a(spr_addr[7:0]),
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.DIA(tb_timstmp[31:16]),
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.ce_a(1'b1),
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.ENA(1'b1),
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.oe_a(1'b1),
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.WEA(tb_enw),
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.do_a(tbts_dat_o),
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.DOA(),
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.clk_b(clk),
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.CLKB(clk),
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.rst_b(rst),
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.RSTB(rst),
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.addr_b(tb_wadr),
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.ADDRB(spr_addr[7:0]),
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.di_b(tb_timstmp),
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.DIB(16'h0000),
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.ce_b(1'b1),
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.ENB(1'b1),
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.we_b(tb_enw)
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.WEB(1'b0),
|
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.DOB(tbts_dat_o[31:16])
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);
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);
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`else
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`else
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|
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assign tbia_dat_o = 32'h0000_0000;
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assign tbia_dat_o = 32'h0000_0000;
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assign tbim_dat_o = 32'h0000_0000;
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assign tbim_dat_o = 32'h0000_0000;
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assign tbar_dat_o = 32'h0000_0000;
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assign tbar_dat_o = 32'h0000_0000;
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assign tbts_dat_o = 32'h0000_0000;
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assign tbts_dat_o = 32'h0000_0000;
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