OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Diff between revs 1011 and 1022

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1011 Rev 1022
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.13  2002/08/28 01:44:25  lampret
 
// Removed some commented RTL. Fixed SR/ESR flag bug.
 
//
// Revision 1.12  2002/08/22 02:16:45  lampret
// Revision 1.12  2002/08/22 02:16:45  lampret
// Fixed IMMU bug.
// Fixed IMMU bug.
//
//
// Revision 1.11  2002/08/18 19:54:28  lampret
// Revision 1.11  2002/08/18 19:54:28  lampret
// Added store buffer.
// Added store buffer.
Line 398... Line 401...
                eear <= #1 32'b0;
                eear <= #1 32'b0;
                esr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
                esr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
                extend_flush_last <= #1 1'b0;
                extend_flush_last <= #1 1'b0;
        end
        end
        else begin
        else begin
 
`ifdef OR1200_CASE_DEFAULT
 
                case (state)    // synopsys parallel_case
 
`else
                case (state)    // synopsys full_case parallel_case
                case (state)    // synopsys full_case parallel_case
 
`endif
                        `OR1200_EXCEPTFSM_IDLE:
                        `OR1200_EXCEPTFSM_IDLE:
                                if (except_flushpipe) begin
                                if (except_flushpipe) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                        extend_flush <= #1 1'b1;
                                        esr <= #1 sr_we ? to_sr : sr;
                                        esr <= #1 sr_we ? to_sr : sr;
Line 512... Line 519...
                        `OR1200_EXCEPTFSM_FLU4: begin
                        `OR1200_EXCEPTFSM_FLU4: begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU5;
                                        state <= #1 `OR1200_EXCEPTFSM_FLU5;
                                        extend_flush <= #1 1'b0;
                                        extend_flush <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0; // damjan
                                        extend_flush_last <= #1 1'b0; // damjan
                                end
                                end
 
`ifdef OR1200_CASE_DEFAULT
 
                        default: begin
 
`else
                        `OR1200_EXCEPTFSM_FLU5: begin
                        `OR1200_EXCEPTFSM_FLU5: begin
 
`endif
                                if (!if_stall && !id_freeze) begin
                                if (!if_stall && !id_freeze) begin
                                        state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                        state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                        extend_flush_last <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0;
                                end
                                end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.