URL
https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Diff between revs 1200 and 1267
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 1200 |
Rev 1267 |
Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
|
|
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
|
|
//
|
// Revision 1.2 2002/10/17 20:04:40 lampret
|
// Revision 1.2 2002/10/17 20:04:40 lampret
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
//
|
//
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
Line 105... |
Line 108... |
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
//
|
//
|
// RAM BIST
|
// RAM BIST
|
//
|
//
|
input mbist_si_i;
|
input mbist_si_i;
|
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
|
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
|
output mbist_so_o;
|
output mbist_so_o;
|
`endif
|
`endif
|
|
|
`ifdef OR1200_NO_IC
|
`ifdef OR1200_NO_IC
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.