OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_if.v] - Diff between revs 617 and 788

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 617 Rev 788
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2002/01/28 01:16:00  lampret
 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
 
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
// Break point bug fixed
Line 78... Line 81...
module or1200_if(
module or1200_if(
        // Clock and reset
        // Clock and reset
        clk, rst,
        clk, rst,
 
 
        // External i/f to IC
        // External i/f to IC
        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
        icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
 
 
        // Internal i/f
        // Internal i/f
        if_freeze, if_insn, if_pc, flushpipe,
        if_freeze, if_insn, if_pc, flushpipe,
        if_stall, no_more_dslot, taken, genpc_refetch, rfe,
        if_stall, no_more_dslot, genpc_refetch, rfe,
        except_itlbmiss, except_immufault, except_ibuserr
        except_itlbmiss, except_immufault, except_ibuserr
);
);
 
 
//
//
// I/O
// I/O
Line 101... Line 104...
//
//
// External i/f to IC
// External i/f to IC
//
//
input   [31:0]                   icpu_dat_i;
input   [31:0]                   icpu_dat_i;
input                           icpu_ack_i;
input                           icpu_ack_i;
input                           icpu_rty_i;
 
input                           icpu_err_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
input   [31:0]                   icpu_adr_i;
input   [3:0]                    icpu_tag_i;
input   [3:0]                    icpu_tag_i;
 
 
//
//
Line 115... Line 117...
output  [31:0]                   if_insn;
output  [31:0]                   if_insn;
output  [31:0]                   if_pc;
output  [31:0]                   if_pc;
input                           flushpipe;
input                           flushpipe;
output                          if_stall;
output                          if_stall;
input                           no_more_dslot;
input                           no_more_dslot;
input                           taken;
 
output                          genpc_refetch;
output                          genpc_refetch;
input                           rfe;
input                           rfe;
output                          except_itlbmiss;
output                          except_itlbmiss;
output                          except_immufault;
output                          except_immufault;
output                          except_ibuserr;
output                          except_ibuserr;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.