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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of all IMMU blocks. ////
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//// Instantiation of all IMMU blocks. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - cache inhibit ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/08/18 19:54:17 lampret
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// Added store buffer.
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//
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// Revision 1.8 2002/08/14 06:23:50 lampret
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// Revision 1.8 2002/08/14 06:23:50 lampret
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// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
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// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
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//
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//
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// Revision 1.7 2002/08/12 05:31:30 lampret
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// Revision 1.7 2002/08/12 05:31:30 lampret
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// Delayed external access at page crossing.
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// Delayed external access at page crossing.
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assign icimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
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assign icimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
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//
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//
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// Cache Inhibit
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// Cache Inhibit
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//
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//
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assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// Cache inhibit is not really needed for instruction memory subsystem.
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// If we would do it, we would do it like this.
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// assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// However this causes a async combinational loop so we stick to
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// no cache inhibit.
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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//
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//
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// Page cross
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// Page cross
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//
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//
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// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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