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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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| Line 73... |
Line 76... |
`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_pic(
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module or1200_pic(
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// RISC Internal Interface
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// RISC Internal Interface
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clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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pic_wakeup, int,
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pic_wakeup, intr,
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// PIC Interface
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// PIC Interface
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pic_int
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pic_int
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);
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);
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Line 93... |
input spr_write; // SPR Write
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input spr_write; // SPR Write
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input [31:0] spr_addr; // SPR Address
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input [31:0] spr_addr; // SPR Address
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input [31:0] spr_dat_i; // SPR Write Data
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input [31:0] spr_dat_i; // SPR Write Data
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output [31:0] spr_dat_o; // SPR Read Data
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output [31:0] spr_dat_o; // SPR Read Data
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output pic_wakeup; // Wakeup to the PM
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output pic_wakeup; // Wakeup to the PM
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output int; // interrupt
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output intr; // interrupt
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// exception request
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// exception request
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//
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//
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// PIC Interface
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// PIC Interface
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//
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//
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Line 155... |
// Write to PICSR, both CPU and external ints
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// Write to PICSR, both CPU and external ints
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//
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//
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`ifdef OR1200_PIC_PICSR
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`ifdef OR1200_PIC_PICSR
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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picsr <= {`OR1200_PIC_INTS-2{1'b0}};
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picsr <= {`OR1200_PIC_INTS{1'b0}};
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else if (picsr_sel && spr_write) begin
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else if (picsr_sel && spr_write) begin
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picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
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picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
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end else
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end else
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picsr <= #1 picsr | um_ints;
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picsr <= #1 picsr | um_ints;
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`else
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`else
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// Unmasked interrupts
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// Unmasked interrupts
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//
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//
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assign um_ints = pic_int & {picmr, 2'b11};
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assign um_ints = pic_int & {picmr, 2'b11};
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//
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//
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// Generate int
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// Generate intr
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//
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//
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assign int = |um_ints;
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assign intr = |um_ints;
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//
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//
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// Assert pic_wakeup when int is asserted
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// Assert pic_wakeup when intr is asserted
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//
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//
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assign pic_wakeup = int;
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assign pic_wakeup = intr;
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`else
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`else
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//
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//
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// When PIC is not implemented, drive all outputs as would when PIC is disabled
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// When PIC is not implemented, drive all outputs as would when PIC is disabled
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//
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//
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assign int = pic_int[1] | pic_int[0];
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assign intr = pic_int[1] | pic_int[0];
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assign pic_wakeup= int;
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assign pic_wakeup= intr;
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//
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//
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// Read PIC registers
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// Read PIC registers
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//
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//
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`ifdef OR1200_PIC_READREGS
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`ifdef OR1200_PIC_READREGS
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