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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Diff between revs 869 and 1130
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| Rev 869 |
Rev 1130 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/06/08 16:19:09 lampret
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// Added generic flip-flop based memory macro instantiation.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Break point bug fixed
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// Break point bug fixed
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| Line 344... |
Line 347... |
.di_b(rf_dataw)
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.di_b(rf_dataw)
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);
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);
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`else
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`else
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`ifdef OR1200_RFRAM_GENERIC
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//
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//
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// Instantiation of generic (flip-flop based) register file
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// Instantiation of generic (flip-flop based) register file
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//
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//
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or1200_rfram_generic rf_a(
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or1200_rfram_generic rf_a(
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// Clock and reset
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// Clock and reset
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| Line 369... |
Line 374... |
.we_w(rf_we),
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.we_w(rf_we),
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.addr_w(rf_addrw),
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.addr_w(rf_addrw),
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.di_w(rf_dataw)
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.di_w(rf_dataw)
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);
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);
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`else
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//
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// RFRAM type not specified
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//
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initial begin
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$display("Define RFRAM type.");
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$finish;
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end
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`endif
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`endif
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`endif
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`endif
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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