URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x8.v] - Diff between revs 1179 and 1184

Rev 1179	Rev 1184
Line 61...	Line 61...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2003/08/11 13:32:19 simons`
	`// BIST interface added for Artisan memory instances.`
	`//`
`// Revision 1.3 2003/04/07 01:19:07 lampret`	`// Revision 1.3 2003/04/07 01:19:07 lampret`
`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`	`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
`//`	`//`
`// Revision 1.2 2002/10/17 20:04:40 lampret`	`// Revision 1.2 2002/10/17 20:04:40 lampret`
`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`	`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
Line 137...	Line 140...

`//`	`//`
`// Internal wires and registers`	`// Internal wires and registers`
`//`	`//`

	`ifdef OR1200_ARTISAN_SSP
	`else
	`ifdef OR1200_VIRTUALSILICON_SSP
	`else
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`assign scanb_so = scanb_si;`	`assign scanb_so = scanb_si;`
`endif	`endif
	`endif
	`endif


`ifdef OR1200_ARTISAN_SSP	`ifdef OR1200_ARTISAN_SSP

`//`	`//`
`// Instantiation of ASIC memory:`	`// Instantiation of ASIC memory:`