OpenCores

Rev 1291	Rev 1582
Line 20...	Line 20...
`//// - Avant! Two-Port Sync RAM (*) ////`	`//// - Avant! Two-Port Sync RAM (*) ////`
`//// - Virage Single-Port Sync RAM ////`	`//// - Virage Single-Port Sync RAM ////`
`//// - Virtual Silicon Single-Port Sync RAM ////`	`//// - Virtual Silicon Single-Port Sync RAM ////`
`//// ////`	`//// ////`
`//// Supported FPGA RAMs are: ////`	`//// Supported FPGA RAMs are: ////`
`//// - Xilinx Virtex RAMB4_S16 ////`	`//// - Xilinx Virtex RAMB16 ////`
	`//// - Xilinx Virtex RAMB4 ////`
`//// - Altera LPM ////`	`//// - Altera LPM ////`
`//// ////`	`//// ////`
`//// To Do: ////`	`//// To Do: ////`
`//// - xilinx rams need external tri-state logic ////`	`//// - xilinx rams need external tri-state logic ////`
`//// - fix avant! two-port ram ////`	`//// - fix avant! two-port ram ////`
Line 61...	Line 62...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2004/06/08 18:15:32 lampret`
	`// Changed behavior of the simulation generic models`
	`//`
`// Revision 1.1 2004/04/08 11:00:46 simont`	`// Revision 1.1 2004/04/08 11:00:46 simont`
`// Add support for 512B instruction cache.`	`// Add support for 512B instruction cache.`
`//`	`//`
`//`	`//`
`//`	`//`
Line 111...	Line 115...
`output [dw-1:0] doq; // output data bus`	`output [dw-1:0] doq; // output data bus`

`//`	`//`
`// Internal wires and registers`	`// Internal wires and registers`
`//`	`//`
	`ifdef OR1200_XILINX_RAMB4
`wire [31:24] unconnected;`	`wire [31:24] unconnected;`
	`else
	`ifdef OR1200_XILINX_RAMB16
	`wire [31:24] unconnected;`
	`endif // !OR1200_XILINX_RAMB16
	`endif // !OR1200_XILINX_RAMB4

`ifdef OR1200_ARTISAN_SSP	`ifdef OR1200_ARTISAN_SSP
`else	`else
`ifdef OR1200_VIRTUALSILICON_SSP	`ifdef OR1200_VIRTUALSILICON_SSP
`else	`else
Line 216...	Line 226...
`.DO({unconnected, doq[23:16]})`	`.DO({unconnected, doq[23:16]})`
`);`	`);`

`else	`else

	`ifdef OR1200_XILINX_RAMB16

	`//`
	`// Instantiation of FPGA memory:`
	`//`
	`// Virtex4/Spartan3E`
	`//`
	`// Added By Nir Mor`
	`//`

	`RAMB16_S36 ramb16_s36(`
	`.CLK(clk),`
	`.SSR(rst),`
	`.ADDR({4'b0000, addr}),`
	`.DI({8'h00, di}),`
	`.DIP(4'h0),`
	`.EN(ce),`
	`.WE(we),`
	`.DO({unconnected, doq}),`
	`.DOP()`
	`);`

	`else

`ifdef OR1200_ALTERA_LPM	`ifdef OR1200_ALTERA_LPM

`//`	`//`
`// Instantiation of FPGA memory:`	`// Instantiation of FPGA memory:`
`//`	`//`
Line 261...	Line 295...
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce && we)`	`if (ce && we)`
`mem[addr] <= #1 di;`	`mem[addr] <= #1 di;`

`endif // !OR1200_ALTERA_LPM	`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16	`endif // !OR1200_XILINX_RAMB16
	`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP	`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP	`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP	`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP	`endif // !OR1200_ARTISAN_SSP

Line 20...

////  - Avant! Two-Port Sync RAM (*)                              ////

////  - Avant! Two-Port Sync RAM (*)                              ////

////  - Virage Single-Port Sync RAM                               ////

////  - Virage Single-Port Sync RAM                               ////

////  - Virtual Silicon Single-Port Sync RAM                      ////

////  - Virtual Silicon Single-Port Sync RAM                      ////

////                                                              ////

////                                                              ////

////  Supported FPGA RAMs are:                                    ////

////  Supported FPGA RAMs are:                                    ////

////  - Xilinx Virtex RAMB4_S16                                   ////

////  - Xilinx Virtex RAMB16                                      ////

////  - Xilinx Virtex RAMB4                                       ////

////  - Altera LPM                                                ////

////  - Altera LPM                                                ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////   - xilinx rams need external tri-state logic                ////

////   - xilinx rams need external tri-state logic                ////

////   - fix avant! two-port ram                                  ////

////   - fix avant! two-port ram                                  ////

Line 61...

Line 62...

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.2  2004/06/08 18:15:32  lampret

// Changed behavior of the simulation generic models

//

// Revision 1.1  2004/04/08 11:00:46  simont

// Revision 1.1  2004/04/08 11:00:46  simont

// Add support for 512B instruction cache.

// Add support for 512B instruction cache.

//

//

//

//

//

//

Line 111...

Line 115...

output  [dw-1:0] doq;    // output data bus

output  [dw-1:0] doq;    // output data bus

//

//

// Internal wires and registers

// Internal wires and registers

//

//

`ifdef OR1200_XILINX_RAMB4

wire [31:24] unconnected;

wire [31:24] unconnected;

`else

`ifdef OR1200_XILINX_RAMB16

wire [31:24] unconnected;

`endif  // !OR1200_XILINX_RAMB16

`endif  // !OR1200_XILINX_RAMB4

`ifdef OR1200_ARTISAN_SSP

`ifdef OR1200_ARTISAN_SSP

`else

`else

`ifdef OR1200_VIRTUALSILICON_SSP

`ifdef OR1200_VIRTUALSILICON_SSP

`else

`else

Line 216...

Line 226...

        .DO({unconnected, doq[23:16]})

        .DO({unconnected, doq[23:16]})

);

);

`else

`else

`ifdef OR1200_XILINX_RAMB16

//

// Instantiation of FPGA memory:

//

// Virtex4/Spartan3E

//

// Added By Nir Mor

//

RAMB16_S36 ramb16_s36(

        .CLK(clk),

        .SSR(rst),

        .ADDR({4'b0000, addr}),

        .DI({8'h00, di}),

        .DIP(4'h0),

        .EN(ce),

        .WE(we),

        .DO({unconnected, doq}),

        .DOP()

);

`else

`ifdef OR1200_ALTERA_LPM

`ifdef OR1200_ALTERA_LPM

//

//

// Instantiation of FPGA memory:

// Instantiation of FPGA memory:

//

//

Line 261...

Line 295...

always @(posedge clk)

always @(posedge clk)

        if (ce && we)

        if (ce && we)

                mem[addr] <= #1 di;

                mem[addr] <= #1 di;

`endif  // !OR1200_ALTERA_LPM

`endif  // !OR1200_ALTERA_LPM

`endif  // !OR1200_XILINX_RAMB4_S16

`endif  // !OR1200_XILINX_RAMB16

`endif  // !OR1200_XILINX_RAMB4

`endif  // !OR1200_VIRTUALSILICON_SSP

`endif  // !OR1200_VIRTUALSILICON_SSP

`endif  // !OR1200_VIRAGE_SSP

`endif  // !OR1200_VIRAGE_SSP

`endif  // !OR1200_AVANT_ATP

`endif  // !OR1200_AVANT_ATP

`endif  // !OR1200_ARTISAN_SSP

`endif  // !OR1200_ARTISAN_SSP

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Diff between revs 1291 and 1582