| Line 20... |
Line 20... |
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Avant! Two-Port Sync RAM (*) ////
|
//// - Virage Single-Port Sync RAM ////
|
//// - Virage Single-Port Sync RAM ////
|
//// - Virtual Silicon Single-Port Sync RAM ////
|
//// - Virtual Silicon Single-Port Sync RAM ////
|
//// ////
|
//// ////
|
//// Supported FPGA RAMs are: ////
|
//// Supported FPGA RAMs are: ////
|
//// - Xilinx Virtex RAMB4_S16 ////
|
//// - Xilinx Virtex RAMB16 ////
|
|
//// - Xilinx Virtex RAMB4 ////
|
//// - Altera LPM ////
|
//// - Altera LPM ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - xilinx rams need external tri-state logic ////
|
//// - xilinx rams need external tri-state logic ////
|
//// - fix avant! two-port ram ////
|
//// - fix avant! two-port ram ////
|
| Line 61... |
Line 62... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.8 2004/06/08 18:15:32 lampret
|
|
// Changed behavior of the simulation generic models
|
|
//
|
// Revision 1.7 2004/04/05 08:29:57 lampret
|
// Revision 1.7 2004/04/05 08:29:57 lampret
|
// Merged branch_qmem into main tree.
|
// Merged branch_qmem into main tree.
|
//
|
//
|
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
|
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
|
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
|
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
|
| Line 140... |
Line 144... |
output [dw-1:0] doq; // output data bus
|
output [dw-1:0] doq; // output data bus
|
|
|
//
|
//
|
// Internal wires and registers
|
// Internal wires and registers
|
//
|
//
|
|
|
|
`ifdef OR1200_XILINX_RAMB4
|
|
wire [1:0] unconnected;
|
|
`else
|
|
`ifdef OR1200_XILINX_RAMB16
|
wire [1:0] unconnected;
|
wire [1:0] unconnected;
|
|
`endif // !OR1200_XILINX_RAMB16
|
|
`endif // !OR1200_XILINX_RAMB4
|
|
|
`ifdef OR1200_ARTISAN_SSP
|
`ifdef OR1200_ARTISAN_SSP
|
`else
|
`else
|
`ifdef OR1200_VIRTUALSILICON_SSP
|
`ifdef OR1200_VIRTUALSILICON_SSP
|
`else
|
`else
|
| Line 273... |
Line 284... |
//
|
//
|
RAMB4_S16 ramb4_s16_0(
|
RAMB4_S16 ramb4_s16_0(
|
.CLK(clk),
|
.CLK(clk),
|
.RST(rst),
|
.RST(rst),
|
.ADDR({2'b00, addr}),
|
.ADDR({2'b00, addr}),
|
.DI({unconnected, di[13:0]}),
|
.DI({2'b00, di[13:0]}),
|
.EN(ce),
|
.EN(ce),
|
.WE(we),
|
.WE(we),
|
.DO({unconnected, doq[13:0]})
|
.DO({unconnected, doq[13:0]})
|
);
|
);
|
|
|
`else
|
`else
|
|
|
|
`ifdef OR1200_XILINX_RAMB16
|
|
|
|
//
|
|
// Instantiation of FPGA memory:
|
|
//
|
|
// Virtex4/Spartan3E
|
|
//
|
|
|
|
RAMB16_S18 ramb16_s18(
|
|
.CLK(clk),
|
|
.SSR(rst),
|
|
.ADDR({4'b0000, addr}),
|
|
.DI({2'b00, di[13:0]}),
|
|
.DIP(2'b00),
|
|
.EN(ce),
|
|
.WE(we),
|
|
.DO({unconnected, doq[13:0]}),
|
|
.DOP()
|
|
);
|
|
|
|
`else
|
|
|
`ifdef OR1200_ALTERA_LPM
|
`ifdef OR1200_ALTERA_LPM
|
|
|
//
|
//
|
// Instantiation of FPGA memory:
|
// Instantiation of FPGA memory:
|
//
|
//
|
| Line 348... |
Line 381... |
always @(posedge clk)
|
always @(posedge clk)
|
if (ce && we)
|
if (ce && we)
|
mem[addr] <= #1 di;
|
mem[addr] <= #1 di;
|
|
|
`endif // !OR1200_ALTERA_LPM
|
`endif // !OR1200_ALTERA_LPM
|
`endif // !OR1200_XILINX_RAMB4_S16
|
`endif // !OR1200_XILINX_RAMB16
|
|
`endif // !OR1200_XILINX_RAMB4
|
`endif // !OR1200_VIRTUALSILICON_SSP
|
`endif // !OR1200_VIRTUALSILICON_SSP
|
`endif // !OR1200_VIRAGE_SSP
|
`endif // !OR1200_VIRAGE_SSP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_ARTISAN_SSP
|
`endif // !OR1200_ARTISAN_SSP
|
|
|
