URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Diff between revs 1200 and 1267

Rev 1200	Rev 1267
Line 61...	Line 61...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
`// Revision 1.5 2003/08/19 16:41:23 simons`	`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
`// Scan signals mess fixed.`	`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
`//`
`// Revision 1.4 2003/08/11 13:32:19 simons`
`// BIST interface added for Artisan memory instances.`
`//`	`//`
`// Revision 1.3 2003/04/07 01:19:07 lampret`	`// Revision 1.3 2003/04/07 01:19:07 lampret`
`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`	`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
`//`	`//`
`// Revision 1.2 2002/10/17 20:04:41 lampret`	`// Revision 1.2 2002/10/17 20:04:41 lampret`
Line 124...	Line 121...
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
`input mbist_si_i;`	`input mbist_si_i;`
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control	input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
`output mbist_so_o;`	`output mbist_so_o;`
`endif	`endif

`//`	`//`
`// Generic synchronous single-port RAM interface`	`// Generic synchronous single-port RAM interface`