| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10.4.9 2004/02/11 01:40:11 lampret
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|
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.10.4.8 2004/01/17 21:14:14 simons
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|
// Errors fixed.
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//
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// Revision 1.10.4.7 2004/01/17 19:06:38 simons
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// Error fixed.
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//
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// Revision 1.10.4.6 2004/01/17 18:39:48 simons
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// Error fixed.
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//
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// Revision 1.10.4.5 2004/01/15 06:46:38 markom
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// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.10.4.4 2003/12/09 11:46:49 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.10.4.3 2003/12/05 00:08:44 lampret
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// Fixed instantiation name.
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//
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// Revision 1.10.4.2 2003/07/11 01:10:35 lampret
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// Added three missing wire declarations. No functional changes.
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//
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// Revision 1.10.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.10 2002/12/08 08:57:56 lampret
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// Revision 1.10 2002/12/08 08:57:56 lampret
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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//
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//
|
// Revision 1.9 2002/10/17 20:04:41 lampret
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// Revision 1.9 2002/10/17 20:04:41 lampret
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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| Line 133... |
Line 160... |
`ifdef OR1200_WB_B3
|
`ifdef OR1200_WB_B3
|
dwb_cti_o, dwb_bte_o,
|
dwb_cti_o, dwb_bte_o,
|
`endif
|
`endif
|
|
|
// External Debug Interface
|
// External Debug Interface
|
dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
|
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
|
dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
|
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
|
|
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
mbist_si_i, mbist_so_o, mbist_ctrl_i,
|
mbist_si_i, mbist_so_o, mbist_ctrl_i,
|
`endif
|
`endif
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| Line 213... |
Line 240... |
|
|
//
|
//
|
// External Debug Interface
|
// External Debug Interface
|
//
|
//
|
input dbg_stall_i; // External Stall Input
|
input dbg_stall_i; // External Stall Input
|
input [dw-1:0] dbg_dat_i; // External Data Input
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|
input [aw-1:0] dbg_adr_i; // External Address Input
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|
input [2:0] dbg_op_i; // External Operation Select Input
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|
input dbg_ewt_i; // External Watchpoint Trigger Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
|
output [3:0] dbg_lss_o; // External Load/Store Unit Status
|
output [1:0] dbg_is_o; // External Insn Fetch Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
|
output [10:0] dbg_wp_o; // Watchpoints Outputs
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output [10:0] dbg_wp_o; // Watchpoints Outputs
|
output dbg_bp_o; // Breakpoint Output
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output dbg_bp_o; // Breakpoint Output
|
|
input dbg_stb_i; // External Address/Data Strobe
|
|
input dbg_we_i; // External Write Enable
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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output [dw-1:0] dbg_dat_o; // External Data Output
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output [dw-1:0] dbg_dat_o; // External Data Output
|
|
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
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|
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
//
|
//
|
// RAM BIST
|
// RAM BIST
|
//
|
//
|
input mbist_si_i;
|
input mbist_si_i;
|
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
|
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
|
output mbist_so_o;
|
output mbist_so_o;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Power Management
|
// Power Management
|
| Line 289... |
Line 318... |
wire icbiu_cyc_ic;
|
wire icbiu_cyc_ic;
|
wire icbiu_stb_ic;
|
wire icbiu_stb_ic;
|
wire icbiu_we_ic;
|
wire icbiu_we_ic;
|
wire [3:0] icbiu_sel_ic;
|
wire [3:0] icbiu_sel_ic;
|
wire [3:0] icbiu_tag_ic;
|
wire [3:0] icbiu_tag_ic;
|
|
wire icbiu_cab_ic;
|
wire [dw-1:0] icbiu_dat_biu;
|
wire [dw-1:0] icbiu_dat_biu;
|
wire icbiu_ack_biu;
|
wire icbiu_ack_biu;
|
wire icbiu_err_biu;
|
wire icbiu_err_biu;
|
wire [3:0] icbiu_tag_biu;
|
wire [3:0] icbiu_tag_biu;
|
|
|
| Line 310... |
Line 340... |
//
|
//
|
wire dmmu_en;
|
wire dmmu_en;
|
wire [31:0] spr_dat_dmmu;
|
wire [31:0] spr_dat_dmmu;
|
|
|
//
|
//
|
// DMMU and DC
|
// DMMU and QMEM
|
//
|
//
|
wire dcdmmu_err_dc;
|
wire qmemdmmu_err_qmem;
|
wire [3:0] dcdmmu_tag_dc;
|
wire [3:0] qmemdmmu_tag_qmem;
|
wire [aw-1:0] dcdmmu_adr_dmmu;
|
wire [aw-1:0] qmemdmmu_adr_dmmu;
|
wire dcdmmu_cycstb_dmmu;
|
wire qmemdmmu_cycstb_dmmu;
|
wire dcdmmu_ci_dmmu;
|
wire qmemdmmu_ci_dmmu;
|
|
|
//
|
//
|
// CPU and data memory subsystem
|
// CPU and data memory subsystem
|
//
|
//
|
wire dc_en;
|
wire dc_en;
|
wire [31:0] dcpu_adr_cpu;
|
wire [31:0] dcpu_adr_cpu;
|
|
wire dcpu_cycstb_cpu;
|
wire dcpu_we_cpu;
|
wire dcpu_we_cpu;
|
wire [3:0] dcpu_sel_cpu;
|
wire [3:0] dcpu_sel_cpu;
|
wire [3:0] dcpu_tag_cpu;
|
wire [3:0] dcpu_tag_cpu;
|
wire [31:0] dcpu_dat_cpu;
|
wire [31:0] dcpu_dat_cpu;
|
wire [31:0] dcpu_dat_dc;
|
wire [31:0] dcpu_dat_qmem;
|
wire dcpu_ack_dc;
|
wire dcpu_ack_qmem;
|
wire dcpu_rty_dc;
|
wire dcpu_rty_qmem;
|
wire dcpu_err_dmmu;
|
wire dcpu_err_dmmu;
|
wire [3:0] dcpu_tag_dmmu;
|
wire [3:0] dcpu_tag_dmmu;
|
|
|
//
|
//
|
// IMMU and CPU
|
// IMMU and CPU
|
| Line 347... |
Line 378... |
wire ic_en;
|
wire ic_en;
|
wire [31:0] icpu_adr_cpu;
|
wire [31:0] icpu_adr_cpu;
|
wire icpu_cycstb_cpu;
|
wire icpu_cycstb_cpu;
|
wire [3:0] icpu_sel_cpu;
|
wire [3:0] icpu_sel_cpu;
|
wire [3:0] icpu_tag_cpu;
|
wire [3:0] icpu_tag_cpu;
|
wire [31:0] icpu_dat_ic;
|
wire [31:0] icpu_dat_qmem;
|
wire icpu_ack_ic;
|
wire icpu_ack_qmem;
|
wire [31:0] icpu_adr_immu;
|
wire [31:0] icpu_adr_immu;
|
wire icpu_err_immu;
|
wire icpu_err_immu;
|
wire [3:0] icpu_tag_immu;
|
wire [3:0] icpu_tag_immu;
|
|
wire icpu_rty_immu;
|
|
|
//
|
//
|
// IMMU and IC
|
// IMMU and QMEM
|
//
|
//
|
wire [aw-1:0] icimmu_adr_immu;
|
wire [aw-1:0] qmemimmu_adr_immu;
|
wire icimmu_rty_ic;
|
wire qmemimmu_rty_qmem;
|
wire icimmu_err_ic;
|
wire qmemimmu_err_qmem;
|
wire [3:0] icimmu_tag_ic;
|
wire [3:0] qmemimmu_tag_qmem;
|
wire icimmu_cycstb_immu;
|
wire qmemimmu_cycstb_immu;
|
wire icimmu_ci_immu;
|
wire qmemimmu_ci_immu;
|
|
|
|
//
|
|
// QMEM and IC
|
|
//
|
|
wire [aw-1:0] icqmem_adr_qmem;
|
|
wire icqmem_rty_ic;
|
|
wire icqmem_err_ic;
|
|
wire [3:0] icqmem_tag_ic;
|
|
wire icqmem_cycstb_qmem;
|
|
wire icqmem_ci_qmem;
|
|
wire [31:0] icqmem_dat_ic;
|
|
wire icqmem_ack_ic;
|
|
|
|
//
|
|
// QMEM and DC
|
|
//
|
|
wire [aw-1:0] dcqmem_adr_qmem;
|
|
wire dcqmem_rty_dc;
|
|
wire dcqmem_err_dc;
|
|
wire [3:0] dcqmem_tag_dc;
|
|
wire dcqmem_cycstb_qmem;
|
|
wire dcqmem_ci_qmem;
|
|
wire [31:0] dcqmem_dat_dc;
|
|
wire [31:0] dcqmem_dat_qmem;
|
|
wire dcqmem_we_qmem;
|
|
wire [3:0] dcqmem_sel_qmem;
|
|
wire dcqmem_ack_dc;
|
|
|
//
|
//
|
// Connection between CPU and PIC
|
// Connection between CPU and PIC
|
//
|
//
|
wire [dw-1:0] spr_dat_pic;
|
wire [dw-1:0] spr_dat_pic;
|
| Line 393... |
Line 452... |
wire du_read;
|
wire du_read;
|
wire du_write;
|
wire du_write;
|
wire [12:0] du_except;
|
wire [12:0] du_except;
|
wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
|
wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
|
wire [dw-1:0] du_dat_cpu;
|
wire [dw-1:0] du_dat_cpu;
|
|
wire du_hwbkpt;
|
|
|
wire ex_freeze;
|
wire ex_freeze;
|
wire [31:0] ex_insn;
|
wire [31:0] ex_insn;
|
|
wire [31:0] id_pc;
|
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
wire [31:0] spr_dat_npc;
|
wire [31:0] spr_dat_npc;
|
wire [31:0] rf_dataw;
|
wire [31:0] rf_dataw;
|
|
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
| Line 408... |
Line 469... |
//
|
//
|
wire mbist_immu_so;
|
wire mbist_immu_so;
|
wire mbist_ic_so;
|
wire mbist_ic_so;
|
wire mbist_dmmu_so;
|
wire mbist_dmmu_so;
|
wire mbist_dc_so;
|
wire mbist_dc_so;
|
|
wire mbist_qmem_so;
|
wire mbist_immu_si = mbist_si_i;
|
wire mbist_immu_si = mbist_si_i;
|
wire mbist_ic_si = mbist_immu_so;
|
wire mbist_ic_si = mbist_immu_so;
|
wire mbist_dmmu_si = mbist_ic_so;
|
wire mbist_qmem_si = mbist_ic_so;
|
|
wire mbist_dmmu_si = mbist_qmem_so;
|
wire mbist_dc_si = mbist_dmmu_so;
|
wire mbist_dc_si = mbist_dmmu_so;
|
assign mbist_so_o = mbist_dc_so;
|
assign mbist_so_o = mbist_dc_so;
|
`endif
|
`endif
|
|
|
|
wire [3:0] icqmem_sel_qmem;
|
|
wire [3:0] icqmem_tag_qmem;
|
|
wire [3:0] dcqmem_tag_qmem;
|
|
|
//
|
//
|
// Instantiation of Instruction WISHBONE BIU
|
// Instantiation of Instruction WISHBONE BIU
|
//
|
//
|
or1200_wb_biu iwb_biu(
|
or1200_iwb_biu iwb_biu(
|
// RISC clk, rst and clock control
|
// RISC clk, rst and clock control
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
.clmode(clmode_i),
|
.clmode(clmode_i),
|
|
|
| Line 517... |
Line 583... |
.mbist_si_i(mbist_immu_si),
|
.mbist_si_i(mbist_immu_si),
|
.mbist_so_o(mbist_immu_so),
|
.mbist_so_o(mbist_immu_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
|
|
// CPU i/f
|
// CPU and IMMU
|
.ic_en(ic_en),
|
.ic_en(ic_en),
|
.immu_en(immu_en),
|
.immu_en(immu_en),
|
.supv(supv),
|
.supv(supv),
|
.icpu_adr_i(icpu_adr_cpu),
|
.icpu_adr_i(icpu_adr_cpu),
|
.icpu_cycstb_i(icpu_cycstb_cpu),
|
.icpu_cycstb_i(icpu_cycstb_cpu),
|
| Line 535... |
Line 601... |
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_immu),
|
.spr_dat_o(spr_dat_immu),
|
|
|
// IC i/f
|
// QMEM and IMMU
|
.icimmu_rty_i(icimmu_rty_ic),
|
.qmemimmu_rty_i(qmemimmu_rty_qmem),
|
.icimmu_err_i(icimmu_err_ic),
|
.qmemimmu_err_i(qmemimmu_err_qmem),
|
.icimmu_tag_i(icimmu_tag_ic),
|
.qmemimmu_tag_i(qmemimmu_tag_qmem),
|
.icimmu_adr_o(icimmu_adr_immu),
|
.qmemimmu_adr_o(qmemimmu_adr_immu),
|
.icimmu_cycstb_o(icimmu_cycstb_immu),
|
.qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
|
.icimmu_ci_o(icimmu_ci_immu)
|
.qmemimmu_ci_o(qmemimmu_ci_immu)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Instruction Cache
|
// Instantiation of Instruction Cache
|
//
|
//
|
| Line 558... |
Line 624... |
.mbist_si_i(mbist_ic_si),
|
.mbist_si_i(mbist_ic_si),
|
.mbist_so_o(mbist_ic_so),
|
.mbist_so_o(mbist_ic_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
|
|
// IC and CPU/IMMU
|
// IC and QMEM
|
.ic_en(ic_en),
|
.ic_en(ic_en),
|
.icimmu_adr_i(icimmu_adr_immu),
|
.icqmem_adr_i(icqmem_adr_qmem),
|
.icimmu_cycstb_i(icimmu_cycstb_immu),
|
.icqmem_cycstb_i(icqmem_cycstb_qmem),
|
.icimmu_ci_i(icimmu_ci_immu),
|
.icqmem_ci_i(icqmem_ci_qmem),
|
.icpu_sel_i(icpu_sel_cpu),
|
.icqmem_sel_i(icqmem_sel_qmem),
|
.icpu_tag_i(icpu_tag_cpu),
|
.icqmem_tag_i(icqmem_tag_qmem),
|
.icpu_dat_o(icpu_dat_ic),
|
.icqmem_dat_o(icqmem_dat_ic),
|
.icpu_ack_o(icpu_ack_ic),
|
.icqmem_ack_o(icqmem_ack_ic),
|
.icimmu_rty_o(icimmu_rty_ic),
|
.icqmem_rty_o(icqmem_rty_ic),
|
.icimmu_err_o(icimmu_err_ic),
|
.icqmem_err_o(icqmem_err_ic),
|
.icimmu_tag_o(icimmu_tag_ic),
|
.icqmem_tag_o(icqmem_tag_ic),
|
|
|
// SPR access
|
// SPR access
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
| Line 596... |
Line 662... |
//
|
//
|
or1200_cpu or1200_cpu(
|
or1200_cpu or1200_cpu(
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
|
|
// Connection IC and IFETCHER inside CPU
|
// Connection QMEM and IFETCHER inside CPU
|
.ic_en(ic_en),
|
.ic_en(ic_en),
|
.icpu_adr_o(icpu_adr_cpu),
|
.icpu_adr_o(icpu_adr_cpu),
|
.icpu_cycstb_o(icpu_cycstb_cpu),
|
.icpu_cycstb_o(icpu_cycstb_cpu),
|
.icpu_sel_o(icpu_sel_cpu),
|
.icpu_sel_o(icpu_sel_cpu),
|
.icpu_tag_o(icpu_tag_cpu),
|
.icpu_tag_o(icpu_tag_cpu),
|
.icpu_dat_i(icpu_dat_ic),
|
.icpu_dat_i(icpu_dat_qmem),
|
.icpu_ack_i(icpu_ack_ic),
|
.icpu_ack_i(icpu_ack_qmem),
|
.icpu_rty_i(icpu_rty_immu),
|
.icpu_rty_i(icpu_rty_immu),
|
.icpu_adr_i(icpu_adr_immu),
|
.icpu_adr_i(icpu_adr_immu),
|
.icpu_err_i(icpu_err_immu),
|
.icpu_err_i(icpu_err_immu),
|
.icpu_tag_i(icpu_tag_immu),
|
.icpu_tag_i(icpu_tag_immu),
|
|
|
// Connection CPU to external Debug port
|
// Connection CPU to external Debug port
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.ex_insn(ex_insn),
|
.ex_insn(ex_insn),
|
|
.id_pc(id_pc),
|
.branch_op(branch_op),
|
.branch_op(branch_op),
|
.du_stall(du_stall),
|
.du_stall(du_stall),
|
.du_addr(du_addr),
|
.du_addr(du_addr),
|
.du_dat_du(du_dat_du),
|
.du_dat_du(du_dat_du),
|
.du_read(du_read),
|
.du_read(du_read),
|
.du_write(du_write),
|
.du_write(du_write),
|
.du_dsr(du_dsr),
|
.du_dsr(du_dsr),
|
.du_except(du_except),
|
.du_except(du_except),
|
.du_dat_cpu(du_dat_cpu),
|
.du_dat_cpu(du_dat_cpu),
|
|
.du_hwbkpt(du_hwbkpt),
|
.rf_dataw(rf_dataw),
|
.rf_dataw(rf_dataw),
|
|
|
|
|
// Connection IMMU and CPU internally
|
// Connection IMMU and CPU internally
|
.immu_en(immu_en),
|
.immu_en(immu_en),
|
|
|
// Connection DC and CPU
|
// Connection QMEM and CPU
|
.dc_en(dc_en),
|
.dc_en(dc_en),
|
.dcpu_adr_o(dcpu_adr_cpu),
|
.dcpu_adr_o(dcpu_adr_cpu),
|
.dcpu_cycstb_o(dcpu_cycstb_cpu),
|
.dcpu_cycstb_o(dcpu_cycstb_cpu),
|
.dcpu_we_o(dcpu_we_cpu),
|
.dcpu_we_o(dcpu_we_cpu),
|
.dcpu_sel_o(dcpu_sel_cpu),
|
.dcpu_sel_o(dcpu_sel_cpu),
|
.dcpu_tag_o(dcpu_tag_cpu),
|
.dcpu_tag_o(dcpu_tag_cpu),
|
.dcpu_dat_o(dcpu_dat_cpu),
|
.dcpu_dat_o(dcpu_dat_cpu),
|
.dcpu_dat_i(dcpu_dat_dc),
|
.dcpu_dat_i(dcpu_dat_qmem),
|
.dcpu_ack_i(dcpu_ack_dc),
|
.dcpu_ack_i(dcpu_ack_qmem),
|
.dcpu_rty_i(dcpu_rty_dc),
|
.dcpu_rty_i(dcpu_rty_qmem),
|
.dcpu_err_i(dcpu_err_dmmu),
|
.dcpu_err_i(dcpu_err_dmmu),
|
.dcpu_tag_i(dcpu_tag_dmmu),
|
.dcpu_tag_i(dcpu_tag_dmmu),
|
|
|
// Connection DMMU and CPU internally
|
// Connection DMMU and CPU internally
|
.dmmu_en(dmmu_en),
|
.dmmu_en(dmmu_en),
|
| Line 695... |
Line 763... |
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_dmmu),
|
.spr_dat_o(spr_dat_dmmu),
|
|
|
// DC i/f
|
// QMEM and DMMU
|
.dcdmmu_err_i(dcdmmu_err_dc),
|
.qmemdmmu_err_i(qmemdmmu_err_qmem),
|
.dcdmmu_tag_i(dcdmmu_tag_dc),
|
.qmemdmmu_tag_i(qmemdmmu_tag_qmem),
|
.dcdmmu_adr_o(dcdmmu_adr_dmmu),
|
.qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
|
.dcdmmu_cycstb_o(dcdmmu_cycstb_dmmu),
|
.qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
|
.dcdmmu_ci_o(dcdmmu_ci_dmmu)
|
.qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Data Cache
|
// Instantiation of Data Cache
|
//
|
//
|
| Line 717... |
Line 785... |
.mbist_si_i(mbist_dc_si),
|
.mbist_si_i(mbist_dc_si),
|
.mbist_so_o(mbist_dc_so),
|
.mbist_so_o(mbist_dc_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
|
|
// DC and CPU/DMMU
|
// DC and QMEM
|
.dc_en(dc_en),
|
.dc_en(dc_en),
|
.dcdmmu_adr_i(dcdmmu_adr_dmmu),
|
.dcqmem_adr_i(dcqmem_adr_qmem),
|
.dcdmmu_cycstb_i(dcdmmu_cycstb_dmmu),
|
.dcqmem_cycstb_i(dcqmem_cycstb_qmem),
|
.dcdmmu_ci_i(dcdmmu_ci_dmmu),
|
.dcqmem_ci_i(dcqmem_ci_qmem),
|
.dcpu_we_i(dcpu_we_cpu),
|
.dcqmem_we_i(dcqmem_we_qmem),
|
.dcpu_sel_i(dcpu_sel_cpu),
|
.dcqmem_sel_i(dcqmem_sel_qmem),
|
.dcpu_tag_i(dcpu_tag_cpu),
|
.dcqmem_tag_i(dcqmem_tag_qmem),
|
.dcpu_dat_i(dcpu_dat_cpu),
|
.dcqmem_dat_i(dcqmem_dat_qmem),
|
.dcpu_dat_o(dcpu_dat_dc),
|
.dcqmem_dat_o(dcqmem_dat_dc),
|
.dcpu_ack_o(dcpu_ack_dc),
|
.dcqmem_ack_o(dcqmem_ack_dc),
|
.dcpu_rty_o(dcpu_rty_dc),
|
.dcqmem_rty_o(dcqmem_rty_dc),
|
.dcdmmu_err_o(dcdmmu_err_dc),
|
.dcqmem_err_o(dcqmem_err_dc),
|
.dcdmmu_tag_o(dcdmmu_tag_dc),
|
.dcqmem_tag_o(dcqmem_tag_dc),
|
|
|
// SPR access
|
// SPR access
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
| Line 751... |
Line 819... |
.dcsb_ack_i(dcsb_ack_sb),
|
.dcsb_ack_i(dcsb_ack_sb),
|
.dcsb_err_i(dcsb_err_sb)
|
.dcsb_err_i(dcsb_err_sb)
|
);
|
);
|
|
|
//
|
//
|
|
// Instantiation of embedded memory - qmem
|
|
//
|
|
or1200_qmem_top or1200_qmem_top(
|
|
.clk(clk_i),
|
|
.rst(rst_i),
|
|
|
|
`ifdef OR1200_BIST
|
|
// RAM BIST
|
|
.mbist_si_i(mbist_qmem_si),
|
|
.mbist_so_o(mbist_qmem_so),
|
|
.mbist_ctrl_i(mbist_ctrl_i),
|
|
`endif
|
|
|
|
// QMEM and CPU/IMMU
|
|
.qmemimmu_adr_i(qmemimmu_adr_immu),
|
|
.qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
|
|
.qmemimmu_ci_i(qmemimmu_ci_immu),
|
|
.qmemicpu_sel_i(icpu_sel_cpu),
|
|
.qmemicpu_tag_i(icpu_tag_cpu),
|
|
.qmemicpu_dat_o(icpu_dat_qmem),
|
|
.qmemicpu_ack_o(icpu_ack_qmem),
|
|
.qmemimmu_rty_o(qmemimmu_rty_qmem),
|
|
.qmemimmu_err_o(qmemimmu_err_qmem),
|
|
.qmemimmu_tag_o(qmemimmu_tag_qmem),
|
|
|
|
// QMEM and IC
|
|
.icqmem_adr_o(icqmem_adr_qmem),
|
|
.icqmem_cycstb_o(icqmem_cycstb_qmem),
|
|
.icqmem_ci_o(icqmem_ci_qmem),
|
|
.icqmem_sel_o(icqmem_sel_qmem),
|
|
.icqmem_tag_o(icqmem_tag_qmem),
|
|
.icqmem_dat_i(icqmem_dat_ic),
|
|
.icqmem_ack_i(icqmem_ack_ic),
|
|
.icqmem_rty_i(icqmem_rty_ic),
|
|
.icqmem_err_i(icqmem_err_ic),
|
|
.icqmem_tag_i(icqmem_tag_ic),
|
|
|
|
// QMEM and CPU/DMMU
|
|
.qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
|
|
.qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
|
|
.qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
|
|
.qmemdcpu_we_i(dcpu_we_cpu),
|
|
.qmemdcpu_sel_i(dcpu_sel_cpu),
|
|
.qmemdcpu_tag_i(dcpu_tag_cpu),
|
|
.qmemdcpu_dat_i(dcpu_dat_cpu),
|
|
.qmemdcpu_dat_o(dcpu_dat_qmem),
|
|
.qmemdcpu_ack_o(dcpu_ack_qmem),
|
|
.qmemdcpu_rty_o(dcpu_rty_qmem),
|
|
.qmemdmmu_err_o(qmemdmmu_err_qmem),
|
|
.qmemdmmu_tag_o(qmemdmmu_tag_qmem),
|
|
|
|
// QMEM and DC
|
|
.dcqmem_adr_o(dcqmem_adr_qmem),
|
|
.dcqmem_cycstb_o(dcqmem_cycstb_qmem),
|
|
.dcqmem_ci_o(dcqmem_ci_qmem),
|
|
.dcqmem_we_o(dcqmem_we_qmem),
|
|
.dcqmem_sel_o(dcqmem_sel_qmem),
|
|
.dcqmem_tag_o(dcqmem_tag_qmem),
|
|
.dcqmem_dat_o(dcqmem_dat_qmem),
|
|
.dcqmem_dat_i(dcqmem_dat_dc),
|
|
.dcqmem_ack_i(dcqmem_ack_dc),
|
|
.dcqmem_rty_i(dcqmem_rty_dc),
|
|
.dcqmem_err_i(dcqmem_err_dc),
|
|
.dcqmem_tag_i(dcqmem_tag_dc)
|
|
);
|
|
|
|
//
|
// Instantiation of Store Buffer
|
// Instantiation of Store Buffer
|
//
|
//
|
or1200_sb or1200_sb(
|
or1200_sb or1200_sb(
|
// RISC clock, reset
|
// RISC clock, reset
|
.clk(clk_i),
|
.clk(clk_i),
|
| Line 792... |
Line 927... |
// RISC Internal Interface
|
// RISC Internal Interface
|
.clk(clk_i),
|
.clk(clk_i),
|
.rst(rst_i),
|
.rst(rst_i),
|
.dcpu_cycstb_i(dcpu_cycstb_cpu),
|
.dcpu_cycstb_i(dcpu_cycstb_cpu),
|
.dcpu_we_i(dcpu_we_cpu),
|
.dcpu_we_i(dcpu_we_cpu),
|
|
.dcpu_adr_i(dcpu_adr_cpu),
|
|
.dcpu_dat_lsu(dcpu_dat_cpu),
|
|
.dcpu_dat_dc(dcpu_dat_qmem),
|
.icpu_cycstb_i(icpu_cycstb_cpu),
|
.icpu_cycstb_i(icpu_cycstb_cpu),
|
.ex_freeze(ex_freeze),
|
.ex_freeze(ex_freeze),
|
.branch_op(branch_op),
|
.branch_op(branch_op),
|
.ex_insn(ex_insn),
|
.ex_insn(ex_insn),
|
|
.id_pc(id_pc),
|
.du_dsr(du_dsr),
|
.du_dsr(du_dsr),
|
|
|
// For Trace buffer
|
// For Trace buffer
|
.spr_dat_npc(spr_dat_npc),
|
.spr_dat_npc(spr_dat_npc),
|
.rf_dataw(rf_dataw),
|
.rf_dataw(rf_dataw),
|
| Line 810... |
Line 949... |
.du_dat_i(du_dat_cpu),
|
.du_dat_i(du_dat_cpu),
|
.du_dat_o(du_dat_du),
|
.du_dat_o(du_dat_du),
|
.du_read(du_read),
|
.du_read(du_read),
|
.du_write(du_write),
|
.du_write(du_write),
|
.du_except(du_except),
|
.du_except(du_except),
|
|
.du_hwbkpt(du_hwbkpt),
|
|
|
// Access to DU's SPRs
|
// Access to DU's SPRs
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
|
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
|
.spr_write(spr_we),
|
.spr_write(spr_we),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_i(spr_dat_cpu),
|
.spr_dat_o(spr_dat_du),
|
.spr_dat_o(spr_dat_du),
|
|
|
// External Debug Interface
|
// External Debug Interface
|
.dbg_stall_i(dbg_stall_i),
|
.dbg_stall_i(dbg_stall_i),
|
.dbg_dat_i(dbg_dat_i),
|
|
.dbg_adr_i(dbg_adr_i),
|
|
.dbg_op_i(dbg_op_i),
|
|
.dbg_ewt_i(dbg_ewt_i),
|
.dbg_ewt_i(dbg_ewt_i),
|
.dbg_lss_o(dbg_lss_o),
|
.dbg_lss_o(dbg_lss_o),
|
.dbg_is_o(dbg_is_o),
|
.dbg_is_o(dbg_is_o),
|
.dbg_wp_o(dbg_wp_o),
|
.dbg_wp_o(dbg_wp_o),
|
.dbg_bp_o(dbg_bp_o),
|
.dbg_bp_o(dbg_bp_o),
|
.dbg_dat_o(dbg_dat_o)
|
.dbg_stb_i(dbg_stb_i),
|
|
.dbg_we_i(dbg_we_i),
|
|
.dbg_adr_i(dbg_adr_i),
|
|
.dbg_dat_i(dbg_dat_i),
|
|
.dbg_dat_o(dbg_dat_o),
|
|
.dbg_ack_o(dbg_ack_o)
|
);
|
);
|
|
|
//
|
//
|
// Programmable interrupt controller
|
// Programmable interrupt controller
|
//
|
//
|
