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Rev 1291	Rev 1582
Line 19...	Line 19...
`//// - Artisan Double-Port Sync RAM ////`	`//// - Artisan Double-Port Sync RAM ////`
`//// - Avant! Two-Port Sync RAM (*) ////`	`//// - Avant! Two-Port Sync RAM (*) ////`
`//// - Virage 2-port Sync RAM ////`	`//// - Virage 2-port Sync RAM ////`
`//// ////`	`//// ////`
`//// Supported FPGA RAMs are: ////`	`//// Supported FPGA RAMs are: ////`
`//// - Xilinx Virtex RAMB4_S16_S16 ////`	`//// - Xilinx Virtex RAMB16 ////`
	`//// - Xilinx Virtex RAMB4 ////`
`//// - Altera LPM ////`	`//// - Altera LPM ////`
`//// ////`	`//// ////`
`//// To Do: ////`	`//// To Do: ////`
`//// - fix Avant! ////`	`//// - fix Avant! ////`
`//// - xilinx rams need external tri-state logic ////`	`//// - xilinx rams need external tri-state logic ////`
Line 60...	Line 61...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2004/06/08 18:15:48 lampret`
	`// Changed behavior of the simulation generic models`
	`//`
`// Revision 1.3 2004/04/05 08:29:57 lampret`	`// Revision 1.3 2004/04/05 08:29:57 lampret`
`// Merged branch_qmem into main tree.`	`// Merged branch_qmem into main tree.`
`//`	`//`
`// Revision 1.2.4.1 2003/07/08 15:36:37 lampret`	`// Revision 1.2.4.1 2003/07/08 15:36:37 lampret`
`// Added embedded memory QMEM.`	`// Added embedded memory QMEM.`
Line 262...	Line 266...
`.DOB(do_b[31:16])`	`.DOB(do_b[31:16])`
`);`	`);`

`else	`else

	`ifdef OR1200_XILINX_RAMB16

	`//`
	`// Instantiation of FPGA memory:`
	`//`
	`// Virtex4/Spartan3E`
	`//`
	`// Added By Nir Mor`
	`//`

	`RAMB16_S36_S36 ramb16_s36_s36(`
	`.CLKA(clk_a),`
	`.SSRA(rst_a),`
	`.ADDRA({4'b0000,addr_a}),`
	`.DIA(di_a),`
	`.DIPA(4'h0),`
	`.ENA(ce_a),`
	`.WEA(we_a),`
	`.DOA(do_a),`
	`.DOPA(),`

	`.CLKB(clk_b),`
	`.SSRB(rst_b),`
	`.ADDRB({4'b0000,addr_b}),`
	`.DIB(di_b),`
	`.DIPB(4'h0),`
	`.ENB(ce_b),`
	`.WEB(we_b),`
	`.DOB(do_b),`
	`.DOPB()`
	`);`

	`else

`ifdef OR1200_ALTERA_LPM_XXX	`ifdef OR1200_ALTERA_LPM_XXX

`//`	`//`
`// Instantiation of FPGA memory:`	`// Instantiation of FPGA memory:`
`//`	`//`
Line 370...	Line 408...
`addr_b_reg <= #1 {aw{1'b0}};`	`addr_b_reg <= #1 {aw{1'b0}};`
`else if (ce_b)`	`else if (ce_b)`
`addr_b_reg <= #1 addr_b;`	`addr_b_reg <= #1 addr_b;`

`endif // !OR1200_ALTERA_LPM	`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16_S16	`endif // !OR1200_XILINX_RAMB16
	`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRAGE_STP	`endif // !OR1200_VIRAGE_STP
`endif // !OR1200_AVANT_ATP	`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SDP	`endif // !OR1200_ARTISAN_SDP

`endmodule`	`endmodule`

Line 19...

////  - Artisan Double-Port Sync RAM                              ////

////  - Artisan Double-Port Sync RAM                              ////

////  - Avant! Two-Port Sync RAM (*)                              ////

////  - Avant! Two-Port Sync RAM (*)                              ////

////  - Virage 2-port Sync RAM                                    ////

////  - Virage 2-port Sync RAM                                    ////

////                                                              ////

////                                                              ////

////  Supported FPGA RAMs are:                                    ////

////  Supported FPGA RAMs are:                                    ////

////  - Xilinx Virtex RAMB4_S16_S16                               ////

////  - Xilinx Virtex RAMB16                                      ////

////  - Xilinx Virtex RAMB4                                       ////

////  - Altera LPM                                                ////

////  - Altera LPM                                                ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////   - fix Avant!                                               ////

////   - fix Avant!                                               ////

////   - xilinx rams need external tri-state logic                ////

////   - xilinx rams need external tri-state logic                ////

Line 60...

Line 61...

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.4  2004/06/08 18:15:48  lampret

// Changed behavior of the simulation generic models

//

// Revision 1.3  2004/04/05 08:29:57  lampret

// Revision 1.3  2004/04/05 08:29:57  lampret

// Merged branch_qmem into main tree.

// Merged branch_qmem into main tree.

//

//

// Revision 1.2.4.1  2003/07/08 15:36:37  lampret

// Revision 1.2.4.1  2003/07/08 15:36:37  lampret

// Added embedded memory QMEM.

// Added embedded memory QMEM.

Line 262...

Line 266...

        .DOB(do_b[31:16])

        .DOB(do_b[31:16])

);

);

`else

`else

`ifdef OR1200_XILINX_RAMB16

//

// Instantiation of FPGA memory:

//

// Virtex4/Spartan3E

//

// Added By Nir Mor

//

RAMB16_S36_S36 ramb16_s36_s36(

        .CLKA(clk_a),

        .SSRA(rst_a),

        .ADDRA({4'b0000,addr_a}),

        .DIA(di_a),

        .DIPA(4'h0),

        .ENA(ce_a),

        .WEA(we_a),

        .DOA(do_a),

        .DOPA(),

        .CLKB(clk_b),

        .SSRB(rst_b),

        .ADDRB({4'b0000,addr_b}),

        .DIB(di_b),

        .DIPB(4'h0),

        .ENB(ce_b),

        .WEB(we_b),

        .DOB(do_b),

        .DOPB()

);

`else

`ifdef OR1200_ALTERA_LPM_XXX

`ifdef OR1200_ALTERA_LPM_XXX

//

//

// Instantiation of FPGA memory:

// Instantiation of FPGA memory:

//

//

Line 370...

Line 408...

                addr_b_reg <= #1 {aw{1'b0}};

                addr_b_reg <= #1 {aw{1'b0}};

        else if (ce_b)

        else if (ce_b)

                addr_b_reg <= #1 addr_b;

                addr_b_reg <= #1 addr_b;

`endif  // !OR1200_ALTERA_LPM

`endif  // !OR1200_ALTERA_LPM

`endif  // !OR1200_XILINX_RAMB4_S16_S16

`endif  // !OR1200_XILINX_RAMB16

`endif  // !OR1200_XILINX_RAMB4

`endif  // !OR1200_VIRAGE_STP

`endif  // !OR1200_VIRAGE_STP

`endif  // !OR1200_AVANT_ATP

`endif  // !OR1200_AVANT_ATP

`endif  // !OR1200_ARTISAN_SDP

`endif  // !OR1200_ARTISAN_SDP

endmodule

endmodule

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Diff between revs 1291 and 1582