| Line 1... |
Line 1... |
/* except.c -- Simulation of OR1K exceptions
|
/* except.c -- Simulation of OR1K exceptions
|
|
|
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
|
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
|
|
Copyright (C) 2008 Embecosm Limited
|
|
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
|
|
|
This program is free software; you can redistribute it and/or modify
|
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation; either version 2 of the License, or
|
|
(at your option) any later version.
|
|
|
|
This program is distributed in the hope that it will be useful,
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
GNU General Public License for more details.
|
|
|
|
You should have received a copy of the GNU General Public License
|
|
along with this program; if not, write to the Free Software
|
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
|
|
|
#include <stdlib.h>
|
|
#include <stdio.h>
|
|
#include <string.h>
|
|
|
|
#include "config.h"
|
This program is free software; you can redistribute it and/or modify it
|
|
under the terms of the GNU General Public License as published by the Free
|
|
Software Foundation; either version 3 of the License, or (at your option)
|
|
any later version.
|
|
|
#ifdef HAVE_INTTYPES_H
|
This program is distributed in the hope that it will be useful, but WITHOUT
|
#include <inttypes.h>
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
#endif
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
more details.
|
|
|
#include "port.h"
|
You should have received a copy of the GNU General Public License along
|
#include "arch.h"
|
with this program. If not, see <http://www.gnu.org/licenses/>. */
|
#include "abstract.h"
|
|
|
/* This program is commented throughout in a fashion suitable for processing
|
|
with Doxygen. */
|
|
|
|
|
|
/* Autoconf and/or portability configuration */
|
|
#include "config.h"
|
|
|
|
/* Package includes */
|
#include "except.h"
|
#include "except.h"
|
#include "sim-config.h"
|
#include "sim-config.h"
|
#include "debug_unit.h"
|
#include "arch.h"
|
#include "opcode/or32.h"
|
|
#include "spr_defs.h"
|
|
#include "execute.h"
|
|
#include "sprs.h"
|
|
#include "debug.h"
|
#include "debug.h"
|
|
#include "spr-defs.h"
|
|
#include "execute.h"
|
|
#include "debug-unit.h"
|
|
|
#if DYNAMIC_EXECUTION
|
#if DYNAMIC_EXECUTION
|
#include "sched.h"
|
#include "sched.h"
|
#include "op_support.h"
|
#include "op_support.h"
|
#endif
|
#endif
|
|
|
|
|
DEFAULT_DEBUG_CHANNEL(except);
|
DEFAULT_DEBUG_CHANNEL(except);
|
|
|
int except_pending = 0;
|
int except_pending = 0;
|
|
|
static const char *except_names[] = {
|
static const char *except_names[] = {
|
| Line 61... |
Line 59... |
"Data TLB Miss",
|
"Data TLB Miss",
|
"Insn TLB Miss",
|
"Insn TLB Miss",
|
"Range",
|
"Range",
|
"System Call",
|
"System Call",
|
"Floating Point",
|
"Floating Point",
|
"Trap" };
|
"Trap"
|
|
};
|
|
|
const char *except_name(oraddr_t except)
|
static const char *
|
|
except_name (oraddr_t except)
|
{
|
{
|
return except_names[except >> 8];
|
return except_names[except >> 8];
|
}
|
}
|
|
|
/* Asserts OR1K exception. */
|
/* Asserts OR1K exception. */
|
/* WARNING: Don't excpect except_handle to return. Sometimes it _may_ return at
|
/* WARNING: Don't excpect except_handle to return. Sometimes it _may_ return at
|
* other times it may not. */
|
* other times it may not. */
|
void except_handle(oraddr_t except, oraddr_t ea)
|
void
|
|
except_handle (oraddr_t except, oraddr_t ea)
|
{
|
{
|
oraddr_t except_vector;
|
oraddr_t except_vector;
|
|
|
if(debug_ignore_exception (except))
|
if(debug_ignore_exception (except))
|
return;
|
return;
|
| Line 90... |
Line 91... |
TRACE("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
|
TRACE("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
|
", cycles %lld, #%lld\n",
|
", cycles %lld, #%lld\n",
|
except, except_name(except), cpu_state.pc, ea, runtime.sim.cycles,
|
except, except_name(except), cpu_state.pc, ea, runtime.sim.cycles,
|
runtime.cpu.instructions);
|
runtime.cpu.instructions);
|
|
|
except_vector = except + (cpu_state.sprs[SPR_SR] & SPR_SR_EPH ? 0xf0000000 : 0x00000000);
|
except_vector =
|
|
except + (cpu_state.sprs[SPR_SR] & SPR_SR_EPH ? 0xf0000000 : 0x00000000);
|
|
|
#if !(DYNAMIC_EXECUTION)
|
#if !(DYNAMIC_EXECUTION)
|
pcnext = except_vector;
|
pcnext = except_vector;
|
#endif
|
#endif
|
|
|
| Line 116... |
Line 118... |
* job at the head of the queue will still have some time remaining) */
|
* job at the head of the queue will still have some time remaining) */
|
if(scheduler.job_queue->time <= 0)
|
if(scheduler.job_queue->time <= 0)
|
do_scheduler();
|
do_scheduler();
|
#endif
|
#endif
|
|
|
switch(except) {
|
switch (except)
|
|
{
|
/* EPCR is irrelevent */
|
/* EPCR is irrelevent */
|
case EXCEPT_RESET:
|
case EXCEPT_RESET:
|
break;
|
break;
|
/* EPCR is loaded with address of instruction that caused the exception */
|
/* EPCR is loaded with address of instruction that caused the exception */
|
case EXCEPT_ITLBMISS:
|
case EXCEPT_ITLBMISS:
|
| Line 142... |
Line 145... |
/* Since these exceptions happen during a simulated instruction and this
|
/* Since these exceptions happen during a simulated instruction and this
|
* function jumps out to the exception vector the scheduler would never have
|
* function jumps out to the exception vector the scheduler would never have
|
* a chance to run, therefore run it now */
|
* a chance to run, therefore run it now */
|
run_sched_out_of_line();
|
run_sched_out_of_line();
|
#endif
|
#endif
|
cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
|
cpu_state.sprs[SPR_EPCR_BASE] =
|
|
cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
|
break;
|
break;
|
/* EPCR is loaded with address of next not-yet-executed instruction */
|
/* EPCR is loaded with address of next not-yet-executed instruction */
|
case EXCEPT_SYSCALL:
|
case EXCEPT_SYSCALL:
|
cpu_state.sprs[SPR_EPCR_BASE] = (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0);
|
cpu_state.sprs[SPR_EPCR_BASE] =
|
|
(cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0);
|
break;
|
break;
|
/* These exceptions happen AFTER (or before) an instruction has been
|
/* These exceptions happen AFTER (or before) an instruction has been
|
* simulated, therefore the pc already points to the *next* instruction */
|
* simulated, therefore the pc already points to the *next* instruction */
|
case EXCEPT_TICK:
|
case EXCEPT_TICK:
|
case EXCEPT_INT:
|
case EXCEPT_INT:
|
cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
|
cpu_state.sprs[SPR_EPCR_BASE] =
|
|
cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
|
#if !(DYNAMIC_EXECUTION)
|
#if !(DYNAMIC_EXECUTION)
|
/* If we don't update the pc now, then it will only happen *after* the next
|
/* If we don't update the pc now, then it will only happen *after* the next
|
* instruction (There would be serious problems if the next instruction just
|
* instruction (There would be serious problems if the next instruction just
|
* happens to be a branch), when it should happen NOW. */
|
* happens to be a branch), when it should happen NOW. */
|
cpu_state.pc = pcnext;
|
cpu_state.pc = pcnext;
|
